考慮多重微影技術之下整數倍列高標準元件的擺置修正技術

Multi-Patterning Aware Detailed Placement Refinement for Designs with Multi-Row Height Cells

陳博揚(Chen, Bo Yang)

指導教授 ： 王廷基

國立清華大學/電機資訊學院/資訊工程學系所/碩士(2017年)

摘要

隨著製程圖案逐漸縮小，與超紫外光微影技術、定向自組裝以及電子束微影技術一樣，多重微影技術已被視為是最有前景的微影技術之一。除此之外，許多不同的標準元件結構也被提出。多層的標準元件結構被用來改善標準元件內部的可繞性；整數倍高的標準元件結構被用來考量耗能、效能以及面積的影響。由於修正擺置時可能會造成其他新的著色衝突，而且移動整數倍高標準元件時可能會在其他列產生元件重疊的情形。基於上述的兩個情形，標準元件的細部擺置問題的難度急遽增加。
在這篇論文中，我們提出了一個修正整數倍高標準元件擺置結果的方法，使得該擺置結果每一層的著色衝突盡量的減少，並且同時減少元件的移動距離。此外我們提出了一個未著色元件群的概念，此概念在修正元件擺置時比著色衝突更加重要。藉由消除未著色元件群而不產生新的著色衝突的方式，我們方法中每個區域修正及全局修正的階段裡未消除的未著色元件群會嚴格的遞減。而實驗結果也顯示了我們的方法可以在合理的時間內迅速地消除幾乎全部的未著色元件群。

關鍵字

多重微影技術 ； 整數倍列高標準元件 ； 多層的標準元件結構 ； 擺置修正技術

並列摘要

As the feature size further decreases, multiple patterning lithography (MPL) has been regarded as one of the most promising lithography solutions, along with extreme ultraviolet lithography (EUVL), directed self-assembly (DSA), and electron beam lithography (EBL). Besides, several different cell structures have been proposed. The cell structure with multiple layers is adopted to improve the intra-cell routability. The use of multi-row height cells has been taken into consideration for power, performance and area concerns. Therefore, the difficulty to refine a cell-based detailed placement increases because of not only the occurrence of new coloring conflicts during refinement but also the cell overlap while shifting multi-row height cells.

In this thesis, we propose a method to refine a given placed design with multi-row height cells and make it have as few coloring conflicts as possible in every layer, while minimizing the total cell displacement. Furthermore, a concept of uncolored cell group (UCG) is presented, which is more important than coloring conflicts during refinement. By eliminating UCGs without generating any new coloring conflict, the number of UCGs strictly decreases in both local and global refinement stages of our method. The experimental results show that our method can eliminate almost all UCGs in a reasonable runtime.

並列關鍵字

multiple patterning lithography ； multi-row height cell structure ； multi-layer cell structure ； Placement Refinement

參考文獻

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[2] K. Yuan, J.-S. Yang, and D. Z. Pan, "Double patterning layout decomposition for simultaneous conict and stitch minimization," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 2, pp. 185~196, 2010.

[4] X. Tang and M. Cho, "Optimal layout decomposition for double patterning technology," in Proceedings of International Conference on Computer-Aided Design, pp. 9~13, 2011.

[5] J.-S. Yang, K. Lu, M. Cho, K. Yuan, and D. Z. Pan, "A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography," in Proceedings of Asia and South Pacific Design Automation Conference, pp. 18~21, 2010.

[6] Y. Xu and C. Chu, "A matching based decomposer for double patterning lithography," in Proceedings of International Symposium on Physical Design, pp. 121~126, 2010.