以高介電層金屬閘堆疊工程製作高遷移率與低等效氧化層厚度之鍺金氧半電晶體研究

High Mobility and Low EOT in Ge MOSFETs Fabricated by Engineering High-k/Metal Gate Stack

黃佳毅(Huang, Jiayi)

指導教授 ： 張廖貴術

國立清華大學/原子科學院/工程與系統科學系/碩士(2017年)

摘要

閘極堆疊工程是提高電晶體性能的重要議題，設計閘極堆疊之時就要同時兼顧EOT的微縮和載子遷移率的退化。通常而言，想要提高金氧半場效電晶體的驅動電流有兩種途徑，一則降低EOT，二則提高載子遷移率。EOT可以通過使用high-k材料來微縮，k值上升，在同樣的物理厚度下EOT就會下降。然而high-k材料與純鍺表面會產生插排，導致其界面缺陷密度太高，如此一來遷移率自然就因為強烈的散射而下降，最終還是導致驅動電流變小。
在本論文的第一部分中，使用氧化鋁緩衝層以鈍化氧化鍺界面層。氧化鋁是一種熱穩定性極佳的材料，可以利用氧化鋁阻擋氧化鍺在高溫下的擴散。比較含有氧化鋁緩衝層和鋁富金屬覆蓋層兩種閘極堆疊電晶體的特性，可以了解到使用氧化鋁緩衝層可以維持較小的遲滯現象，較低的界面缺陷密度以及較高的遷移率。以GeOx/Al2O3 /HfON /TiN作為閘極堆疊的電晶體取得了記錄中最高的遷移率，其值為655 cm2/V·s。
而在論文第二部分中，討論了氧空缺在high-k材料不同深度對漏電流和EOT的影響。氧空缺是利用Zr-rich覆蓋層引入到high-k材料當中的。在結合第一章氧化鋁緩衝層之作用的情況下，氧空缺位於high-k材料下方靠近鍺界面的電晶體擁有最佳的轉換特性和遷移率。而氧空缺位於high-k材料中央及靠近閘電極的電晶體，雖然強烈的微縮了EOT，但是閘極漏電流也大到無法接受。使用GeOx/Al2O3 /HfON /TiN 閘極堆疊的電晶體取得了~6.4 Å的EOT，閘極漏電密度約為 10-5μA/cm2，開關電流的比例約為3.5個數量級，次臨界斜率約為130mV/dec，遷移率高達 618 cm2/V·s。
論文的第三部分主要利用不同閘電極材料改善了頻率分散的問題並降低了閘極漏電流。這部分使用原子層沉積的TiN、HfN和ZrN來減少邊界缺陷、抑制漏電流。尤其是ALD沉積的HfN和ZrN，將閘極漏電流壓制了四個數量級。最終頻率分散被減小到很輕微。與此同時，極佳的性能仍然被保持，其次臨界斜率僅為120 mV/dec而導通電流高達10 μA/μm。

關鍵字

鍺 ； 電晶體 ； 高介電係數 ； 遷移率 ； 漏電流 ； 閘極堆疊 ； 界面 ； 金屬覆蓋層 ； 氧化鋯

並列摘要

Gate stack engineering is a big issue of Ge MOSFETs to realizing high performance. The consideration of EOT scaling and mobility degradation should be taken during the fabrication of gate stack. Two ways are generally proposed to enhance the drive current of a MOSFET, namely, a smaller equivalent oxide thickness (EOT) and a higher carrier mobility. The EOT can be scaled down by high dielectric constant (k value) gate oxide materials, thus the MOS capacitance is increased. However, the interface state density and defect may be induced by the lattice mismatch of Ge and high-k. Besides, the carrier mobility would be decreased by the higher scattering effects, which eventually lead to the degradation of device drive current.
A gate stack with Al2O3 buffer layer(BL) is proposed to passivate GeO2 IL in the first part of this thesis. Al2O3 is a material with excellent thermal stability. The diffusion of GeOx can be suppressed by Al2O3 BL. By comparing electrical characteristics of MOSFETs with Al2O3 BL and Al-rich capping layer, some effect was clarified. The MOS capacitor with Al2O3 BL maintains better hysteresis, lower interface trap density and the MOSFETs with Al2O3 BL achieved higher hole mobility. A record high mobility of 655 cm2/Vs was achieved with GeOx/Al2O3 /HfON /TiN gate stack. The interface was passivated by the Al2O3 BL.
Effects on EOT and gate leakage of oxygen vacancy at different depth of high-k gate dielectric are studied in the second part. Oxygen vacancy was introduced into high-k material by Zr-rich capping layer. Combining the passivation of Al2O3 BL, the MOSFET with vacancy close to Ge achieved excellent transfer characteristics and mobility. The EOT is aggressively scaled by bulk vacancy and vacancy near to gate electrode, but the leakage is also too high. An EOT of ~6.4 Å, gate leakage current density of ~10-5μA/cm2, ON/OFF ratio=3.5 orders, S.S. of 130mV/dec, mobility of 618 cm2/Vs in Ge pMOSFET is achieved by GeOx/Al2O3 /Zr-rich/ZrO2 /TiN gate stack.
The frequency dispersion is eased and gate leakage is suppressed by various gate electrode materials in the third part. Atomic layer deposited TiN, HfN and ZrN was applied to decrease the border trap and reduce the leakage. The gate leakage was suppressed down by ALD HfN and ZrN for 4 orders. The dispersion was eventually become slight. At the same time, an excellent performance of ~120 mV/dec S.S. and ~10 μA/μm drive current is obtained.

並列關鍵字

Ge ； MOSFET ； high-k ； mobility ； interface ； leakage ； ZrO2

參考文獻

[1] P.Zimmerman et al., “High performance Ge pMOS devices using a Si-compatible process flow,” Technical Digest - International Electron Devices Meeting, IEDM. pp. 1–4, 2006.

[2] C.-H.Fu et al., “Enhanced Hole Mobility and Low Tinv for pMOSFET by a Novel Epitaxial Si/Ge Superlattice Channel,” IEEE Electron Device Letters, vol. 33, no. 2. pp. 188–190, 2012.

[3] S.Maikap, M. H.Lee, S. T.Chang, andC. W.Liu, “Characteristics of strained-germanium p- and n-channel field effect transistors on a Si (1 1 1) substrate,” Semicond. Sci. Technol., vol. 22, no. 4, pp. 342–347, 2007.

[4] W. P.Bai, N.Lu, andD. L.Kwong, “Si interlayer passivation on germanium MOS capacitors with high-k dielectric and metal gate,” IEEE Electron Device Letters, vol. 26, no. 6. pp. 378–380, 2005.

[5] J. H.Stathis andD. J.DiMaria, “Reliability projection for ultra-thin oxides at low voltage,” International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), no. 3. pp. 167–170, 1998.