晶片網路快取記憶體索引方法使閒置路由器數量最大化

晶片網路因具有高度平行化和易擴充等特性，被廣泛使用於多核心系統下處理器之間的溝通。其中路由器負責處理器間資料的傳遞，扮演了重要的角色，然而其在閒置的狀態下仍有相當可觀的靜態功率消耗。為了解決此問題，常見的做法是對路由器使用功率閘控，當路由器沒有被使用時關閉其電源，藉此降低靜態功率消耗。為提升功率閘控的效率，我們提出快取記憶體索引方法，針對不同應用選擇適合的索引方法，使得晶片網路上路由器的閒置時間最大化。實驗結果顯示，藉由我們提出的快取記憶體索引方法平均可以使得晶片網路上的路由器閒置時間增加78.9%。

關鍵字

晶片網路；快取記憶體索引；降低靜態功率

並列摘要

Network-on-chip (NoC) has been adopted as fast and efficient communication infrastructures in multi-core system for years. The on-chip routers play an important role in providing communication among cores. However, the routers consume considerable leakage power even if they are not in use. Applying power-gating to on-chip routers is a feasible approach to reduce the leakage power consumption. To take full advantage of router power-gating, we hope that the sleep period of routers can be as longer as possible. We propose a cache indexing algorithm such that accessing cache has the minimal impact on interrupting the sleep of idle routers. Experimental results show that our proposed method increases the sleep time of on-chip routers by 78.9% in average.

並列關鍵字

NoC ； cache indexing ； leakage power reduction

參考文獻

[1] Lizhong Chen, Di Zhu, Massoud Pedram, and Timothy Mark Pinkston. Simulation of noc power-gating: Requirements, optimizations, and the agate simulator. J. Parallel Distrib. Comput., 95:69–78, 2016.

[2] Lizhong Chen and Timothy Mark Pinkston. Nord: Node-router decoupling for effective power-gating of on-chip routers. In 45th Annual IEEE/ACM International Symposium

[7] Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, and Daihan Wang. Run-time power gating of on-chip routers using look-ahead routing. In Proceedings of the 13th Asia

[9] Tony Givargis. Zero cost indexing for improved processor cache performance. ACM Trans. Design Autom. Electr. Syst., 11(1):3–25, 2006.

[11] Xiaowen Chen, Zhonghai Lu, Axel Jantsch, and Shuming Chen. Supporting distributed shared memory on multi-core network-on-chips using a dual microcoded controller. In

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晶片網路快取記憶體索引方法使閒置路由器數量最大化

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