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  • 學位論文

半導體研發設計階段以WAT參數建構系統化黃金晶方抽樣分析模型

A Systematic Golden Die Sampling Analysis Model with WAT Parameters at Semiconductor R&D Stage

指導教授 : 陳飛龍 劉淑範

摘要


自從台灣發展高科技產業以來,經過數十年的發展,已經成為台灣高產值的產業之一,特別是在半導體產業上的成就已成為各國學習與競爭的目標。由於半導體生產的高度複雜以及對於時間上的急切性,迫使晶圓廠必須透過各種分析以及製程監控等方法來加速晶圓的生產以維持市場優勢並提升顧客以及公司的競爭力,特別是在新產品或製程研發階段,在此階段由於研發人員利用WAT測試晶圓來測試顧客所提供的電路設計,在無歷史資料可參考的情況下,僅能透過全測的方式收集大量的資料並透過研發人員的經驗以及工程背景知識來判斷,找出較為符合目標的晶方,而龐大的數據資料往往耗費研發人員大量的時間並造成不同人員對於黃金晶方判斷上的差異,因此本研究建構半導體研發階段WAT參數之黃金晶方抽樣分析,經由資料轉換萃取、模糊自我適應共振理論網路(Fuzzy ART)、向量內積計算相似性這幾個流程,經由晶方的群聚分析、相似性分析後決定出具代表性的抽樣晶方,提供給研發人員找出黃金晶方以及群聚,利用黃金晶方群聚的WAT資料回饋,以提升製程分析的效率。經由半導體廠所提供之實證資料的分析,本研究能有效的將參數資料分成適當的群聚,接著透過相似性分析,決定各個群聚代表的晶方,做為資料分析的抽樣目標,以找出接近黃金晶方的目標晶方和其所在的群聚,提供該階段產線研發人員未來晶圓製程分析的參考依據。

並列摘要


Semiconductor industry has one of the most productive industries in Taiwan and been the role model for other countries to be competitive in this field. Due to the complex manufactory processes and limited time to meet market demands maintain high yield, silicon wafer FAB must use variable analyses and process monitering methods to improve the process efficiency, especially at the stage of new product development, engineer have to test circuit design for customers with wafer acceptance test (WAT). However, it’s time-consuming to collect data so huge amount of for determining golden die and sometimes mistakes could be made due to the different diagnose methods and experiences form engineers. This paper is to develop an approach for WAT parameter sampling analysis of golden die through data extraction and transformation at semiconductor R&D stage, Fuzzy ART, and similarity analysis. The most representative sampling die can be determined through die cluster and similarity analysis and then it can be used for engineers to find golden die corresponding with experiments on those date provided by semiconductor companies, the presented approach classifieds data into suitable clusters and the representative die for each cluster can then be selected via similarity analysis. Therefore, we can determine the die closest to the golden die and the group. This may provide engineers with information useful for that stage manufacturing to which it belongs to process analysis in the future.

參考文獻


游淑敏,2008,「以WAT 參數資料建構半導體研發設計階段黃金晶方群聚分析」,國立清華大學工業工程與工程管理研究所碩士論文。
魏連均,2006,「應用類神經網路建構晶圓圖故障圖樣辨識模式」,國立清華大學工業工程與工程管理研究所碩士論文。
Allan, Y. W., 1996. “A Statistical Parametric and Probe Yield Analysis Methodology” Defect and Fault Tolerance in VLSI Systems. Proceedings., IEEE International Symposium on 131-139
Alfredo, W., Michael, A. A., Amanda, A., 2002. “The Neural Simulation Language: A System for Brain Modeling” The MIT Press; illustrated edition edition
Bose, B. K., 2007. “Neural network applications in power electronics and motor drives: An introduction and perspective” IEEE Transactions on Industrial Electronics, 54, 14-33.

被引用紀錄


鄭禮欣(2011)。以模糊自適應共振理論網路建構晶圓針測圖與缺陷圖之關聯模式分析〔碩士論文,國立清華大學〕。華藝線上圖書館。https://doi.org/10.6843%2fNTHU.2011.00161

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