Incremental Floorplanning for I/O Signal Skew Improvement

針對輸入輸出訊號歪斜的平面規劃漸進式改良方法

羅毅揚(Yi-Yang Luo)

指導教授 ： 麥偉基

國立清華大學/電機資訊學院/資訊工程學系/碩士(2011年)

https://doi.org/10.6843/NTHU.2011.00505

摘要

在這篇論文中，我們提出了一個以線性規劃為基礎的漸進式平面規劃來最小化覆晶式設計的輸入輸出訊號歪斜。在線性規劃的模型中，我們加入了三種不同類型的限制條件。拓撲學的限制條件用來維持平面規劃的合法性。計算歪斜的限制條件用來計算輸入輸出訊號歪斜的量。當最小化歪斜的時候，使用約束線長的限制條件來約束線長的增加量。實驗結果顯示出使用漸進式平面規劃對於輸入輸出訊號歪斜可以有10%到31%的改善並且總線長的增加量可以被控制在可接受的範圍中甚至是獲得改善。

關鍵字

漸進式平面規劃 ； 輸入輸出訊號歪斜

並列摘要

In this thesis, we propose a linear programming-based incremental floorplanning algorithm
to minimize the I/O signal skew for flip-chip design. In the linear programming, we add
three types of constraints. The topological constraints are used to keep the legality of the
floorplan. The skew evaluation constraints are used to evaluate the I/O signal skew. The
wirelength restriction constraints are used to restrict wirelength increase when minimizing
the skew. Experimental results show that I/O signal skew can be improved from 10% to
31%, and the increase of total wirelength can be controlled in an acceptable range or even
improved.

並列關鍵字

Incremental floorplanning ； I/O signal skew

參考文獻

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[14] L. Huang, Y. Cai, Q. Zhou, X. Hong, J. Hu, Y. Lu, “Clock Network Minimization

[1] C.-Y. Wang, W.-K. Mak, “Signal skew aware floorplanning and bumper signal assignment

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