Investigation of Traps in MOS structure by Charge Pumping Technique

電荷汲引技術對於MOS結構中缺陷分析和調控

董烈廷(Lieh-Ting Tung)

指導教授 ： 洪銘輝 ； 郭瑞年

國立清華大學/工學院/材料科學工程學系/碩士(2008年)

摘要

二氧化矽在矽基板上的電晶體元件尺寸的微小化，已經逼近了其量子穿隧的極限，材料具備高界電係數的特性使其成為具有潛力的取代材料，然而高界電常數之界電材料與矽基板鍵結的缺陷以及材料上本質的差異，造成了金屬氧化物場效應電晶體的電晶體特性退化，因此具有極高電子的電子或電洞遷移率的半導體材料應用在作為電晶體之基板，成為了下一個世代的半導體產業的新希望。
然而，然而高界電常數之界電材料與基板鍵結的缺陷以及材料上本質的差異，在成了電晶體特性上的損害，因此有效率並且準確的將缺陷量化並且了解缺陷的深度分布以及跟能量的關係，利用各種分析的技術去探究缺陷的屬性以能夠了解元件退化的原因，成為了日後電晶體特性進步的主要關鍵。
在本文中，吾者利用電荷汲引技術，有效地並準確地量化缺陷，了解其分佈，並設法降低缺對電晶體的影響。

關鍵字

缺陷 ； 電荷汲引技術 ； 電晶體 ； 高電子遷移率 ； 高界電常數

並列摘要

Atomic-layer-deposited (ALD) high κ dielectric Al2O3 film on In0.53Ga0.47As, using Al(CH3)3 (TMA) and H2O as the precursors, was demonstrated low interfacial density of states (Dit) ~ 2.5x1011 by the charge pumping method for the first time after a dopant activation at RTA 650oC in N2. The depth profile of border-trap density in gate dielectric and low densities of bulk trap (Nbt) ~ 7x1019 cm-3 are obtained by the relationship between Qcp and frequency. Low Dit and Nbt represent excellent interfacial property and oxide quality in employing ALD-Al2O3 as gate dielectric on In0.53Ga0.47As. Besides, energy dependence of Dit is extracted with modulating the rise/fall time of gate pulse.
The interfacial properties were through understood with the application of charge pumping and HR-TEM. The density of interfacial trap, variation of bulk trap densities, and energy dependence of interfacial trap density were extraction. These evidences might indicate the theory: the intense trap features suggest that the interface between these two oxides contains a significant defect concentration and the origin may have to do with the fact that the Y cation in Y2O3 is trivalent, and the Hf cation in HfO2 is tetravalent, thus, leading to dissimilar charge distributions near the interface as likely sites for defects. In this way, the traps at interface or near interface can be absorbed to the interface between Y2O3 and HfO2, owing to dielectric materials of dissimilar cation valences, which raised an important possibility of tailoring the trap locations in a gate dielectric stack. Maybe, this work, thus, has raised an important possibility of tailoring the trap locations in a gate dielectric stack through multilayering a number of dielectric materials of dissimilar cation valences.

並列關鍵字

Trap ； Charge pumping method ； Transistor ； High Mobility ； HASH(0x1bf54350)

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