基於模擬退火法之邏輯匣尺寸和閥值電壓的選派任務達到漏電功率最小化

Leakage Power Minimization using Simulated-Annealing-Based Gate Sizing and Threshold Voltage Assignment

游智詮

指導教授 ： 林永隆

國立清華大學/電機資訊學院/資訊工程學系/碩士(2013年)

https://doi.org/10.6843/NTHU.2013.00147

摘要

在此論文當中，針對邏輯匣尺寸和閥值電壓的選派任務，提出一個漏電流最小化的設計方法。在現今電子產品強調高效能和低耗能的趨勢下，節省電能的消耗已是熱門議題，其中漏電流的節約更是重要的因素。因此選用適當的邏輯匣尺寸和閥值電壓，不僅能夠達到高效能的需求，同時可以降低漏電流值。
為了達到漏電值的最小化，本論文以模擬退火法為基礎的演算法，結合遞迴性演算法作為初始值。另外，為探索足夠的解空間及尋找最佳化的解，實作計時器以快速計算訊號到達時間與需求時間的差異值。實驗結果顯示，此設計方法能夠在效能限制的條件中有效降低漏電流值。

關鍵字

Simulated-Annealing-Based ； Gate Sizing ； Threshold Voltage Assignment ； Leakage Power Minimization

並列摘要

We propose an iterative (IR) and simulated-annealing (SA) based methodology for leakage power minimization by the means of gate sizing and threshold voltage assignment. Currently, there is a strong market for high-performance mobile devices to have low power consumption. Among many low power consumption oriented design techniques, leakage power minimization is one of the key technologies. For cell-based design, gate sizing and threshold voltage assignment can be employed to meet timing requirement while reducing total leakage power. We apply simulated-annealing-based optimization on an initial solution that is generated by an iterative algorithm. In order to explore more solution space, we implement a timing engine for fast calculation of timing slack. Experimental results show that the proposed methodology can effectively reduce leakage power under performance constraints.

參考文獻

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