使用機率性最小和演算法之全平行高速低密度奇偶檢查碼解碼器架構

對一個全平行高速低密度奇偶檢查碼解碼器(LDPC codes)而言，要達到高速(High Throughput)則必須將硬體內速度慢電路架構加以改進，所以我們提出機率性正規化最小和演算法(Probabilistic Normalized Min-Sum Algorithm)，將查核節點(Check Node)內比較出第一小第二小的電路，改成只需比較出第一小與機率式的第二小的架構，利用此架構在遞迴(iteration)次數最多為7次的情況下，我們可以只犧牲0.05dB的位元錯誤率(bit error rate,BER)，但卻可以得到最長路徑(Critical Path)變短與面積下降的好處，且我們根據最佳的正規化因子(Normalized factor)等於0.5和比較器電路改用查表的方式實作，可以實現出3bit硬體電路與4bit的位元錯誤率，然後再採用同時處理兩個字碼(codeword)的硬體架構和提早終止解碼機制(Early Termination)來實作。我們以TSMC 90nm 1P9M COMS製程來實作，APR(Automatic Place and Routing)後面積為7.97 mm^2，吞吐量(Throughput)為223.8(Gbps)，吞吐量與面積的比率(TAR)為28.08(Gbps/mm^2)，且與5bit的TPMP架構相比我們可以有62%的面積化簡與78.7%的最長路徑化簡。

關鍵字

低密度奇偶檢查碼；機率性最小和演算法；高速

並列摘要

In this thesis, we propose a Probabilistic Normalized Min-Sum Algorithm (PNMSA) for low-density parity-check (LDPC) decoders, where a probabilistic second minimum value is used in the check-node processing. Simulation results show that the proposed algorithm only introduces a minor performance degradation compared to the original normalized Min-Sum Algorithm. Based on the PNMSA, a fully-parallel decoder architecture is devised, where the check-node processing is implemented using several subunits and an efficient method is proposed to exchange messages between these subunits. With a carefully-chosen normalization factor, a satisfactory error-rate performance can be achieved using a lower number of quantization bits. In addition, look-up-table-based comparison with lower complexity is used to implement the check-node units. The proposed decoder was implemented using a 90-nm 1P9M CMOS process. Post-layout results show that the decoder occupies an area of 7.97 mm^2, achieves a throughput of 223.8-Gbps, and an energy efficiency of 14.9 pJ/bit.

並列關鍵字

LDPC ； Probabilistic Min-Sum Algorithm ； High-Throughput

參考文獻

[21] C.-C. Lin, K.-L. Lin, H.-C. Chang, and C.-Y. Lee, “A 3.33Gbps (1200,720) low-density parity check code decoder,”Solid-State Circuits Conference, pp. 211-214, Sep. 2005.

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[2] D. J. C. Mackay and R.M. Neal, “Near Shannon limit performance of low density parity check codes,”Electron. Letters, vol. 33, no. 6, pp. 457-458, Jun. 1997.

[3] D. J. C. MacKay, “Good error-correcting codes based on very sparse matrices,“ IEEE Trans. Inf. Theory, vol. 45, no. 2, pp. 399-431, Mar. 1999.

[6] R. M. Tanner, “A recursive approach to low-complexity codes,” IEEE Trans. Inf. Theory, vol. IT-27, no. 5, pp. 533-547, Sep. 1981.

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使用機率性最小和演算法之全平行高速低密度奇偶檢查碼解碼器架構

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