通用圖形處理器內晶片網路之動態頻率調整機制

Run-Time Frequency Scaling of On-Chip Networks for GPGPU

杜巧韻(Chiao-Yun Tu)

指導教授 ： 金仲達

國立清華大學/電機資訊學院/資訊工程學系/碩士(2013年)

https://doi.org/10.6843/NTHU.2013.00707

摘要

現今的通用圖形處理器(GPGPUs) 於高度平行的應用程式上能提供相較於一般用途處理器 (CPU) 十倍甚至百倍的運算能力。由於通用圖形處理器於晶片網路(Network-on-Chip)上所表現的傳輸行為模式與一般用途處理器不同，傳統設計給一般用途處理器的晶片網路架構並不適用給通用圖形處理器。此碩士論文中提出了一個動態頻率調整機制，根據晶片網路處理的負荷量調整網路頻率以符合不同應用程式對於頻寬的需求。
在此碩士論文裡，首先，我們探討通用圖形處理器在網路的傳輸行為模式並將它們分成三種類型。在不同的類型下，需求網路和回覆網路由於網路負載量的差異會有不同的頻寬需求。其次，我們動態的監控某些運算核心(shader core)並預測網路的負荷量，再依據前面研究階段的類型特徵去調節網路頻率。實驗結果顯示此動態頻率調節機制最高可以提升二十七百分比的性能(平均能夠提升七點四百分比的性能)。

關鍵字

通用圖形處理器 ； 晶片網路 ； 動態頻率調整

並列摘要

Modern General Purpose computing on GPUs (GPGPUs) provide orders of magnitude more computing power than general purpose processors (CPU) for highly parallel applications. Since the traffic pattern of GPGPUs behaves considerably different than CPU, the conventional interconnection network designs for CPU are not applicable for GPGPUs. This thesis proposes a run-time dynamic frequency scaling mechanism that can meet the bandwidth demands of different applications by tuning the frequency of network in response to the network load. In this thesis, we first investigate the characteristics of GPGPU traffic pattern and classify the traffic patterns of GPGPUs to three types. Under the different types, the request network and reply network require different bandwidth to handle the network load. Second, we leverage the property to regulate the network
frequency dynamically by monitoring some shader cores and predict the network load. Evaluation show that this dynamic frequency tuning design can achieve up to 27% improvement compared to baseline setting (on average, it results 7.4 % improvement).

並列關鍵字

GPGPU ； Network-On-Chip ； Dynamic Frequency Scaling ； Many-to-Few-to-Many

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