加寬匯流排的動態隨機存取記憶體之三維修復架構

3D Redundancy Architecture for Wide-I/O DRAM

江宛庭

指導教授 ： 吳誠文

國立清華大學/電機資訊學院/電機工程學系/碩士(2013年)

https://doi.org/10.6843/NTHU.2013.00783

摘要

三維堆疊架構近年來已成為高集成度電子系統的新興技術，且有高資料頻寬及低功耗的特性，整體架構通常由記憶體和邏輯晶片組成，其中大容量記憶體的良率往往會比邏輯晶片低，所以針對記憶體設計有效的測試及修復機制在維持良率上更是扮演不可或缺的角色。在此篇論文中，我們針對加寬匯流排的動態隨機存取記憶體發展兩種不同的三維修復架構，分別稱為CRA1和CRA2，兩者最主要的差別在於備份記憶體的類型及擺放位置，在第一種架構中，各層動態隨機存取記憶體皆有備份記憶體，其類型為動態隨機存取記憶體，且可修復三維堆疊架構中的任一層；第二種架構中，我們將備份記憶體配置在最底層的邏輯晶片上，其類型為靜態隨機存取記憶體，同樣可修復三維堆疊架構中的任一層。
在實驗中，我們實作了硬體架構並與傳統修復架構(TRA)比較，分析不同修復架構的修復率及所需面積，第一個實驗觀察共用不同層備份記憶體對修復率有何影響，實驗結果發現修復率在可共用備份記憶體的情況下，可達到最多3%的成長，但是所需的面積跟傳統修復架構相同。第二個實驗觀察將備份記憶體放置在各層晶片上和放置在最底層邏輯晶片上的影響，實驗結果發現後者可使用少於前者40%的備份記憶體來達到與之相同的修復率，但由於後者的備份記憶體設計上較有彈性，所以相對要多付出1.27%面積的代價。

關鍵字

三維堆疊架構 ； 加寬匯流排 ； 動態隨機存取記憶體 ； 記憶體修復 ； 記憶體測試 ； 良率

並列摘要

The three-dimensional integrated circuit (3D IC) is considered a promising approach that can obtain high data band-width and low power consumption for future electronic systems that require high integration level. One of the popular drivers for 3D IC is the integration of a memory stack and a logic die. Because the yield of a 3D IC is the product of respective yields of the mounted dies, the yields of the memory dies and logic die must be high enough, or the 3D IC will be too expensive to be manufactured. It is generally agreed that the yield of large memories that are manufactured with advanced technologies is lower than the logic die. As a consequence, to obtain a high yield of 3D ICs, efficient test and repair methodologies for memories are necessary. In this thesis, we target the wide-I/O dynamic random access memory (DRAM) and propose two 3D redundancy architectures, i.e., Cubical Redundancy Architectures 1 and 2 (CRA1 and CRA2). In CRA1, spares are associated with each DRAM die as in a conventional 2D architecture. In CRA2, we use a static random access memory (SRAM) on the logic die as spares.
We implemented both CRA1 and CRA2, and compared their repair rates as well as area overhead with the traditional redundancy architecture (TRA). Experimental results show that the CRA1 can obtain up to 3% higher stack yield than the TRA with the same area overhead. On the other hand, the CRA2 can obtain the same yield as the CRA1 with 40% less spares, but 1.27% higher area overhead than the CRA1.

並列關鍵字

3D IC ； wide-I/O ； DRAM ； memory repair ； memory testing ； yield

參考文獻

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