透過您的圖書館登入
IP:3.141.100.120
  • 學位論文

具有電容不匹配校正之 2.4 GHz數位控制震盪器

A 2.4-GHz Digitally Controlled Oscillator with Capacitance Mismatch Calibration

指導教授 : 謝志成

摘要


摘要   本論文為設計一個應用於 2.4 GHz 工業/科學/醫療之2.4 GHz 頻段數位控制震盪器。由於我們在電路的設計階段無法預測在實際的操作裡,來自於實體電路的製作、電路的工作電壓和每一次工作環境 (PVT)總共會貢獻多少變化量。,此不確定因素使得操作於開迴路之震盪器不適用於許多應用裝置上。為消除以上的缺點限制,在此論文裡提出一個具有校正不匹配效應能力之數位控制震盪器。   此論文所提出的架構包括一個數位控制震盪器、一個能擷取震盪器頻率資訊的計數器、電容不匹配量化計算器及校正後震盪器控制碼產生器。在此震盪器裡我們使用對電容做開關的方式來當作電路裡的可變電容,使得震盪器訊號較能抵抗來自於類比雜訊干擾的操作環境。計數器負責將我們震盪器的震盪頻率回饋給電容不匹配量化計算器以用於得知多少誤差存在於我們的被控制單元。當得到足夠的誤差資訊後,控制碼產生器則能依照此資訊來產生對應於使用者所需之震盪訊號的校正後控制碼來調控此電路的震盪器。   此論文的電路設計將實現於台灣積體電路製造股份有限公司所提供的互補式金屬氧化層半導體 0.18 微米製程。全部的總電路大小是 1 × 1 平方毫米。從量測結果顯示,此震盪器的震盪範圍約為 2.28 ~ 2.42 GHz。在距離載波500 kHz之相位雜訊能量低於載波能量 101 dB。此數位控制震盪器所能提供的解析度大約是七個控制碼,消耗的功率約為 13 毫瓦。

關鍵字

震盪器 數位 校正

並列摘要


Abstract In this thesis, a digitally controlled oscillator (DCO) designed for 2.4 GHz Industrial, Science, and Medical band (ISM-band) application is proposed. As the non-ideal effects due to process, supply voltage and temperature (PVT) variations, the DCO is not ideally controlled. This makes DCO open-loop operation unsuitable for most applications. By applying capacitance mismatch calibration, it is possible to accurately control the DCO frequency. Therefore, the above limit no longer exists. The proposed design consists of a digital controlled oscillator (DCO), a ripple counter, a mismatch calculator and a calibrated code generator. By adopting switched-capacitor arrays as varactor, the DCO oscillation frequency is stable and robust against analog noise. The counter estimates this oscillation frequency and feedback it to the mismatch calculator to find the capacitance variation. After variation values are obtained, the calibrated code generator could transfer the desired oscillation frequency into a best-fitted DCO control code. This design is implemented in TSMC 0.18 μm 1P6M CMOS process and the chip area is 1 × 1 mm2. According to the measurement results, the oscillating frequency is 2.28 ~ 2.42 GHz with total 140 MHz tuning range. The phase noise at 500-kHz frequency offset is less than -101 dBc/Hz. The frequency resolution is about 7 bits and the total power consumption is about 13 mW from an 1.8-V power supply.

並列關鍵字

oscillator digital calibrate

參考文獻


[7] Zhenbiao Li and Kenneth K. O, “A Low-Phase-Noise and Low-Power Multiband
[12] Robert Bogdan Staszewski, Senior Member, IEEE., John L.Wallberg, Sameh Rezeq, Chih-Ming Hung, Member, IEEE, Oren E. Eliezer, Member, IEEE, Sudheer K. Vemulapalli, Member, IEEE, Chan Fernando, Ken Maggio, Member, IEEE, Roman Staszewski, Member, IEEE, Nathen Barton, Meng-Chang Lee, Member, IEEE, Patrick Cruise, Mitch Entezari, Khurram Muhammad, and Dirk Leipold, “All-Digital PLL and Transmitter for Mobile Phones”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005
[5] Pao-Lung Chen, Member, IEEE, Ching-Che Chung, Member, IEEE, Jyh-Neng Yang, Member, IEEE, and Chen-Yi Lee, Member, IEEE., “A Clock Generator With Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range Applications”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 6, JUNE 2006
[6] Robert Bogdan Staszewski and Poras T. Balsara, “Phase-Domain All-Digital Phase-Locked Loop”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 52, NO. 3, MARCH 2005
[8] Marc Tiebout, Member, IEEE, “Low-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 7, JULY 2001

延伸閱讀