應用於28奈米高介電常數金屬閘極邏輯製程之自我對準氮化矽一次性寫入記憶體

A Self-Aligned Nitride Based Logic Nonvolatile OTP Cell in 28nm High-k Metal Gate CMOS Technology

宋昱德(Yuh-Te Sung)

指導教授 ： 林崇榮

國立清華大學/電機資訊學院/電子工程研究所/碩士(2014年)

摘要

近十年來半導體產業的爆炸性發展，使得可攜帶的個人化電子裝置更加普及。為了滿足資料在失去電源供應後仍能保存的需求，非揮發性記憶體(Nonvolatile Memory, NVM)所扮演的角色愈趨重要。同時，非揮發性記憶體正逐漸朝向內嵌式的晶片發展，如此一來便能有效降低電路板的面積，使得電子產品更加輕薄、更具有競爭力。然而在90nm製程以後，在傳統非揮發性記憶體中占有主流地位的快閃記憶體遭受了製程微縮上的挑戰。原因包括閘極氧化層漏電流、極高的操作電壓、電容耦合與過大的面積等等，進而使其在發展上受限。且傳統的非揮發性記憶體元件並不相容於邏輯製程，繁瑣製程的步驟不但衝擊著良率與可靠度，更造成整合上的困難並使製造成本節節上升。
然而本篇論文則是提出另一種非揮發一次性寫入(One-Time Programmable, OTP)記憶體元件，其相容於一般的邏輯製程，不須增加額外的光罩。此元件是將兩個串聯電晶體的閘極互相靠近，使其本身的間隙壁(spacer)融合在一起，產生了自我對準的氮化矽(Self-Aligned Nitride, SAN)作為電荷之儲存區，稱之為SAN記憶體元件。元件採用源極注入機制(Source-Side Injection, SSI)作為寫入操作，並利用選擇閘極(Select Gate, SG)與寫入閘極(Program Gate, PG)控制。另外，可利用帶對帶熱電洞(Band-to-Band Hot Holes, BBHH)進行抹除操作以探討此OTP多次性寫入(Multi-Time Programmable, MTP)的可能性。
SAN記憶體元件符合低功率、製程簡易、面積小等優點，且因其是以氮化矽作為儲存的介質，與傳統的浮閘極快閃記憶體相比，閘極氧化層厚度的下降不會造成嚴重的漏電問題，因此在未來製程的微縮上具有很大的競爭優勢。

關鍵字

非揮發性記憶體 ； 自我對準氮化矽 ； 邏輯製程相容 ； 嵌入式記憶體

並列摘要

Semiconductor manufacturing technology has evolved drastically in past decades, resulting in the popularization of personal and portable electronic devices. Almost all electronic devices need Non-Volatile Memory (NVM) to meet storage requirement since important information need to be kept when power is cut off. Meanwhile, single NVM memory chip is converted into embedded NVM (eNVM) chip gradually. Hence, the area of circuits can be reduced efficiently, making electronic products lighter, thinner and more competitive. Nevertheless, Flash memory, which composes mainstream of NVM products, has confronted lots of challenges in 90nm technology and beyond, including gate oxide leakage, high operation voltage, capacitive coupling and oversized area. Besides, comparing to pure logic process, traditional NVM devices require a dozen of masks and additional process steps, which will rising costs, and leads to yield and reliability concerns.
However, this thesis has presented another novel One-Time Programmable (OTP) memory cell, fully compatible with CMOS logic process, thus it does not need any additional mask. This memory cell is fabricated by placing two series gates as close as possible. By doing so, Self-Aligned Nitride (SAN) is formed by the merged spacer of two series transistor, as charge storage node; therefore, it is named SAN memory cell. The SAN cell uses Source-Side Injection (SSI) as program mechanism, which is controlled by Program Gate (PG) and Select Gate (SG). Band-to-Band Hot Holes (BBHH) as erase mechanism are also discussed for the evaluation of Multi-Time Programmable (MTP) operation.
SAN memory cell has exhibited its excellent features of low power, simple process and small area. Moreover, since Silicon Nitride is used as storage material instead of Poly Silicon, the gate oxide thickness can be reduced further. This makes SAN memory cell be promising candidate in scaled technologies.

並列關鍵字

Nonvolatile Memories (NVMs) ； Self-Aligned Nitride (SAN) ； Logic Compatible ； Embedded NVMs (eNVMs)

參考文獻

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