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  • 學位論文

臨界電壓可調式之可三維堆疊嵌入式源/汲極超薄通道電晶體

Vth tunable embedded source/drain epi-like Si FETs for 3D sequential integration

指導教授 : 吳孟奇 楊智超
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摘要


這篇論文提出了使用尖峰式雷射結晶(Pulse Laser Crystallization)技術,成長出高品質的多晶矽材料,稱之為“類晶矽”(epi-like Si),而其低熱預算的特性(<450℃)相當利於發展累加型三維堆疊元件及晶片。伴隨者化學機械研磨技術我們亦成功的製做出三維堆疊式50nm 節點超薄通道(T_Si=14nm) n/p-金氧半場效電晶體,而其具有較陡峭的次臨界擺幅(88 and 121 mV/dec.)和較高的開路電流,相較於未經過化學機械研磨減薄的元件(T_Si=50nm),不僅有較佳的電特性外更也能在高溫操作下,保有元件的優異特性。 藉由材料的分析,我們亦可發現雷射退火技術可使非晶矽薄膜轉換為具1000 nm晶粒之多晶矽薄膜。同時利用化學機械研磨可將其表面平均粗糙度由37A降低為5A,透過拉曼光譜和XRD分析其他屬性也將在論文裡面討論。 當元件尺寸不斷的微縮,源/汲極區高接觸電阻將使得元件的驅動電流降低,而本技術提出之背電極自我對準嵌入式源/汲極的結構,可藉由提升源/汲極的厚度,進而有效的降低接觸電阻,相較於無嵌入式源/汲極的結構的元件,此結構可有效提升元件的驅動電流約20%~30%。 另一方面,在低熱預算及高元件性能之基礎下,我們也提出一種具有獨立的背閘極(BG)的元件結構應用〖3D〗^+-IC,使得元件之臨界電壓可更容易地被調整往正或負方向位移,即使是奈米線的通道寬度(WFin)被縮小到只有20nm,(這將使得更難以背電極控制元件臨界電壓),此結構仍然有相當高的臨界電壓控制力,可由高臨界電壓調整因子得知(γ>0.05)。此外,由於量子侷限效應,納米線通道還帶來了另一個優勢,即此元件對溫度變化相對較不敏感,如此具有高臨界電壓調整因子及低溫度敏感度(low temperature sensitivity)之嵌入式源/汲極矽奈米線場效電晶體,在積層型三維堆疊元件集成電路上,可實現低的閉路電流和高的驅動電流的理想操作特性。

並列摘要


Sequential layered integration technology that can fabricate 3D sequentially stacked CMOS low thermal budget process (<450oC) is proposed in this article. With green laser crystallized epi-like Si, chemical mechanical polish (CMP), and surface modification processes for thin channel fabrication, 3D stackable 50nm node ultra-thin body (T_Si=14nm) n/p-MOSFETs with steep subthreshold swings (88 and 121 mV/dec.) and high on-currents (121 and 62 μA/μm) are demonstrated. Not only the transfer characteristics are better than the devices without CMP thinning processes (T_Si=50nm) but they are less sensitive to the temperature. Therefore, we can find that the large-grained laser crystallized channel (grain size~1000nm), followed by a novel super-CMP- planarization process (reducing the mean roughness from 37A to 5A) play a core technology in this thesis, and the other properties of film are identified by Raman and XRD diffraction pattern. In order to solve high contact resistance which will reduces drive current (Ion) of device as feature size keeps scaling, we proposed the structure with embedded Source and Drain (e-S/D) to increases the thickness of source and drain region to reduce contact resistance. In this structure, the drive currents have improvements of 20 to 30% compared to the device without e-S/D. Finally, we combine this structure with independent back gate (BG), V_th adjusters for 3D sequential integrated circuit are also realized by low thermal budget process. With additional back gate structure, UTB devices can offer flexible controllability in threshold voltage (V_th) with large γ (body factor>0.05) even though the W_Fin of channel is shrunk to 20nm, and we can also get larger body factor by changing the material of back gate with low resistance. Thanks to the quantum confinement effect, such V_th adjustable nanowire devices perform well at higher temperatures, which give a wide design window for 3D sequential integrated circuit.

參考文獻


[43] 凃政暉,「微晶矽薄膜電晶體及記憶體元件」,國立交通大學,碩士論文, 民國101年。
[28] Vasilis Pavlidis,Eby Friedman, Three-dimensional Integrated Circuit Design, P50
[50] Jean-Pierre Colinge , Multiple-gate SOI MOSFETs, Solid-State Electronics 48 (2004) 897–905 Department of Electrical and Computer Engineering, University of California, Davis, CA 95616, USA
[1] Y. C. Lien et al., “3D Ferroelectric-like NVM/CMOS Hybrid Chip by sub-400oC Sequential Layered Integration”, International Electron Devices Meeting (IEDM) Tech. Dig., p. 33.6, 2012.
[3] W. C. Chen et al., “In Situ Doped Source/Drain for Performance Enhancement of Double-Gated Poly-Si Nanowire Transistors”, IEEE Trans. Electron Devices, vol. 55, no. 7, pp. 1608, Jan. 2010.

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