SONOS記憶元件之模擬與模型研究

中文摘要近年來非揮發性記憶體元件在半導體記憶元件的發展與研究上，其所扮演著越來越重要的角色。而且隨著可攜帶式電子商品的普及化，例如：筆記型電腦、行動電話和隨身記憶卡….等，非揮發性記憶元件在製程技術、結構、操作機制和電路佈局都有著快速的進步。從最早的唯讀記憶體(Read Only Memory, ROM)、可程式唯讀記憶體(Programmable Read Only Memory, PROM)，到可抹除程式化唯讀記憶體(Erasable Programmable Read Only Memory, EPROM)、電性可抹除程式化唯讀記憶體(Electrically Erasable Programmable Read Only Memory, EEPROM)，以至目前最熱門的快閃記憶體(Flash Memory)，非揮發性記憶體在其結構上亦隨之不斷的再改變。然而，近來矽-氧化矽-氮化矽-氧化矽-矽(Silicon- Oxide-Nitride-Oxide-Silicon, SONOS)記憶體元件受到相當大的注意，主要是因為SONOS記憶體元件跟COMS製程有著相當高的整合性，且一個元件可以達到兩個位元的效果，所以可以大大地降低生產成本。本論文是以矽離子注入SONOS記憶元件之參數萃取為主，並且使用TSUPREM4和MEDICI兩套軟體對SONOS元件做製程及電性上的模擬。從模擬中可以發現使用通道熱電子注入來做寫入是具有區域性儲存的特性(Localized Trapping)，這在做多位元記憶上有相當大的助益。並利用模擬在順向讀出(Forward Read)和反向讀出(Reverse Read)的差異上做比較後，可以得知採用通道熱電子注入和反向讀出可以達到單一元件有兩個位元的效果。在參數萃取方面，是採用BSIM3v3這套軟體來調整參數使其模擬出來的電性能較符合實際量測的值，並且是以讀出條件時的電流值能越準確為主。最後萃取出來的參數能藉由HSPICE的模擬而判別元件是(0,0)、(0,1)、(1,0)或是(1,1)的狀態。

關鍵字

SONOS記憶元件；參數萃取； BSIM3v3模擬

並列摘要

Abstract Recently, Non-Volatile Memory (NVM) devices play important roles permanent in development and investigation of memory devices. And the portable electrical merchandises are popularization, for example: notebook, cellular phone and memory card etc.. The NVM devices advance fast in fabrication technology, structure, operation condition and circuit layout. The structure of NVM devices is improved from ROM and PROM to EPROM, EEPROM and Flash Memory. However, SONOS memory devices are taken a big notice recently because of its complete compatibility with existing advanced CMOS technology. Besides, it also can cost down because that it can achieve two-bit per cell. This thesis is based on “Parameter Extraction of Si-implanted SONOS Memory Devices” and using TSUPREM4 with MEDICI to simulate the cell. During simulation, using channel hot electron injection to program possesses localized trapping characterization. The forward read and reverse read are compared during simulation. The parameter extraction is used BSIM3v3 to fit all ID-VG curve. Finally, using HSPICE simulates these parameters and the simulated value of read current can be differentiated the (0, 0), (0, 1), (1, 0) and (1, 1) state.

並列關鍵字

SONOS Memory Device ； Parameter Extraction ； BSIM3v3 Simulation

參考文獻

[1] Toshiba Corporation ULSI Research Center, “Technology Trend of Flash-EEPROM —Can Flash-EEPROM overcome DRAM?”, Symposium on VLSI Technology Digest of Technical Papers, 1992, pp.6~9.

[2] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices”, Bell Syst. Tech. J., Vol. 46, 1967, pp. 1283.

[3] Wegener H. A. R. et al., “The variable threshold transistor, a newly electrically alterable nondestructive read-only storage device”, IEDM Tech. Dig., 1967.

[4] F. Masuoka, M. Asano, H. Iwahashi, T. Komuro and S. Tanaka, “A new Flash EEPROM cell using triple polysilicon technology”, IEEE Tech. Dig. IEDM, 1984, pp. 464~467.

[5] G. Samachisa, C.-S. Su, Y.-S. Kao, G. Smarandoiu, C.-Y. M. Wang, T. Wong and C. Hu, “A 128K Flash EEPROM using double-polysilicon technology”, IEEE J. Solid-State Circuit, Vol. SC-22, No. 5, 1987, pp.676~682.

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SONOS記憶元件之模擬與模型研究

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