使用時鐘閘複製技術建構時鐘樹

在現今高效能的超大型積體電路設計中，降低整體功率消耗為目前設計電路的重要課題。時鐘閘的技術已被廣泛應用來降低電路上功率的消耗，當某段電路處於閒置狀態時，只要將時鐘閘關閉便可節省功率的耗損。而先前的研究指出當時鐘閘的數量越少，能減少晶片的面積亦能增加時鐘樹的可繞度。本篇論文提出了一個有三步驟的時鐘閘優化方法，藉由正反器分群和合併時鐘閘的方法，建構出一個較少時鐘閘及緩衝器數量的時鐘閘樹。此外根據時鐘閘下游所包含之正反器數量，我們推導出一個參數用來調整時鐘閘及緩衝器的數量比。本篇論文演算法中的三個步驟：(1) 對正反器做分群、(2) 對電路做時序的合法化、(3) 優化結果。在第一個步驟中將晶片根據線長分成三個區域，在三個區域中用不同的分群方式對正反器做分群；第二個步驟為了使電路符合整備時間限制，使用合併的方法對時鐘閘及其扇出正反器之間做合併，並且在合併的過程中同時減少時鐘閘及緩衝器數量；最後一個步驟則針對第二個步驟的結果，以時鐘閘及其扇出正反器的群重心對鄰近群做合併，以達到更有效地減少目標函數的目的。藉由實驗數據可以發現，本論文所提出之方法可有效地在各個步驟中減少時鐘閘及緩衝器之數量，且推導出的參數對於不同的輸入參數，可有效地調整時鐘閘與緩衝器的數量比，達到最佳化目標函數的目的。

關鍵字

時鐘樹；時鐘閘；整備時間

並列摘要

The power consumption is always an important issue in high performance VLSI design. Clock gating technique has been used widely to reduce the power consumption in clock circuit design. By simply shutting off a part of clock gating cells during the idle state, designer can easily reduce the power consumption. Previous research has shown that fewer clock gating cell can benefit the area and the routability of clock circuit. In this paper, we propose a three-phase clock gating optimization approach by using clustering and merging algorithm to construct a gated clock tree with minimal number of clock gating cells and buffers. In addition, according to the fan-out numbers of a clock gating cell, we derive a parameter  that can be used to adjust the tradeoff between clock gating cell and buffer. Our three-phase algorithm described below (1) flip-flop clustering (2) clock gating cell legalization (3) solution refinement. In the first phase we split the die into three regions and clustering flip-flops with different strategy in each region. After the first phase, we can get an initial solution which is not meeting the setup-time constraint. Therefore, in the second phase, we propose two methods to fix the setup-time constraint and also reduce the number of clock gating cells and buffers. In the final phase, we will merge each nearby clock gating cell if the result can improve our cost function. Experimental results show that our proposed approach can reduce the number of clock gating cells and buffers in each phase. Moreover, the well-defined parameter derived by input parameter  can adjust the tradeoff between clock gating cell and buffer efficiently.

並列關鍵字

clock tree ； clock gating ； setup time

參考文獻

[3] T. Sakurai, H. Kawaguchi, T. Kuroda, ”Low-power CMOS design through VTH

Workshop on VLSI'99, 1999.

[2] M. Hansson, A. Alvandpour, “A low clock load conditional flip-flop,” in

Proceedings of the IEEE International SOC Conference, 2004.

on Low Power Electronics and Design, 1997.

國際替代計量

使用時鐘閘複製技術建構時鐘樹

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