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  • 學位論文

在功率限制下功率矽穿孔考量之三維積體電路分割演算法

Power TSV Aware Three Dimensional Intergrated Circuits Partitioning under Power Constraints

指導教授 : 陳美麗

摘要


在三維積體電路架構的設計流程當中,電路分割是很重要的一個課題,在晶片設計的過程當中,各個邏輯閘擺放分層的位置,將會影響矽穿孔(Through Silicon Via, TSV)數量、電路成本、良率及散熱問題,尤其當輸入功率越來越高的時候,散熱會變的更加困難,而且也會需要更多傳導功率用的功率矽穿孔(Power TSV)。因此如何找到一個分割結果,能使得晶片在power density限制之下,最小化矽穿孔之總數及Area Overhead就成為一個很重要的課題,本篇論文提出一個在功率限制下可最小化功率矽穿孔之三維積體電路分割的方法。 在本篇論文中,我們會先分析並計算電路的功率,得到每個邏輯閘各別的功率後,則可以由各層所有邏輯閘的總功率來計算出需要多少的功率矽穿孔,並且在除以各層之總面積之後可以得到各層的功率密度。我們會以multilevel的架構來對電路進行連續地coarsening,藉此降低電路的複雜度。然後在不違反功率密度限制的前提下對電路進行初始分割,接著對初始分割後的電路交錯執行uncoarsening和K-layer-Two-way FM partitioning來降低矽穿孔之總數並最佳化其結果。 在實驗結果中,我們使用了2011年IC/CAD競賽所提供的Benchmarks[1],並比較了在各種不同的功率輸入下,使用不同cost function之分割後的結果。最後可以得知,分割時有加入功率矽穿孔之考量的分割結果,其矽穿孔之總數皆少於未考量功率矽穿孔之分割的結果。

關鍵字

三維積體電路 功率 矽穿孔

並列摘要


In 3D IC Design, partition is an important step problem in physical design. The partition results of netlist will affect the number of Through Silicon Via (TSV), circuit cost, yield and thermal dissipation. Especially when the input frequency is higher, thermal dissipation will be difficult too. And that means more number of power TSV will be needed. Therefore, to find a partition result that can minimize TSV and total area overhead under power density constraint becomes an import issue. In this paper we propose a power TSV aware three dimensional integrated circuits partitioning under power constraints algorithm. First of all, we analyze the power of a circuit. Then we can calculate the power of every logic gate. After that, we can calculate how many power TSV will be needed in each layer by the total power of logic gate on each layer. And power density of each layer equals total cell power divided by the total area of each layer. We use a multilevel framework to coarsen the netlist successively to reduce the complexity of the netlist. Then we get an initial partition result that satisfies power density constraint. Based on this initial partition result, we use Uncoarsening and K-layer-Two-way FM partitioning algorithm to refine our partition result. As shown in the experimental, we show the result of different cost function under several different input frequency. And the number of total TSV when partitioning with power TSV consideration is less than partitioning without power TSV consideration.

並列關鍵字

3DIC TSV power

參考文獻


[21] 薛祖雲, “電路分割方法相關研究與應用於電路擺置之電路分割演算法” , 中原大學資訊工程研究所碩士論文 , 2011.
[20] 吳偉傑, “考量功率限制之三維積體電路分割演算法” , 中原大學資訊工程研究所碩士論文 , 2011.
[18] T. Y. Hsueh, H. C. Lai, H. L. Chang, M. C. Chi, “An Effective Power-Aware Partitioning Algorithm for 3D IC Designs” , 22th VLSI Design/CAD Symposium, 2011.
[2] D. Kung, R. Puri, "CAD Challenges for 3D ICs," in Proc. Asia and South Pacific Design Automation Conference, 2009.
[4] G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar “Multilevel Hypergraph Partitioning: Application in VLSI Domain”, in Proc. ACM/IEEE Design Automation Conference, pp.526-529, 1997.

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