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  • 學位論文

應用於擺置階段之低功耗導向雙重電壓源配置方法

A Low Power Driven Voltage Scaling Algorithm Using Dual Supply Voltage at Placement Stage

指導教授 : 陳美麗

摘要


隨著製程技術的進步發展,IC產業進入深次微米時代,單一晶片中可容納的元件也大幅的增加,功率消耗成為我們設計上的一個重要的考量。減少功率消耗的方法中,降低供給電壓是目前的一個趨勢,然而在實體的設計上卻還未有成熟發展。因此本論文中,我們提出一個演算法”應用於擺置階段之低功耗導向雙重電壓源配置方法”, 以探討擺置與雙重電壓源配置方法的關係,此論文中我們將分為三個步驟:首先是時序導向與基本的力導向擺置階段,我們以力導向演算法(Force Directed Algorithm)[1]建立出實體設計電路初始擺置位置,直到每個元件達到力平衡的位置並依照標準元件的相對位置來擺置元件直到所有元件都擺置在列上並且彼此沒有重疊。第二步驟是電壓源配置階段階段,我們優先配置距離高電壓供給源(high voltage power source)較遠並且能改善較多的功率消耗的標準元件於低電壓供給,直到無法再有任何功率消耗改善。最後的步驟則是高低電壓列的建立及時序的改善階段,我們會根據電壓源配置後的高低電壓元件分佈的結果,建立出高低電壓列的位置,並且將元件擺置於相對應的列中。並且檢查時序是否正確符合需求,由於時序的正確與否,關係晶片是否能正常運作,因此我們使用gate sizing的方式修正違反時序限制的元件,以保證時序的正確性。 實驗結果顯示,使用基本的力導向擺置執行我們的電壓源配置方法與電壓源配置前比較,平均可改善功率消耗45.1%;時序導向擺置執行我們的電壓源配置方法與電壓源配置前比較,平均上則可改善功率消耗45.6%。而應用於商業軟體的擺置上執行我們的電壓源配置方法與電壓源配置前比較,也能達到平均36.7%的功率消耗改善。

並列摘要


With the improvement in the process technology, IC industry enters the deep sup-micron era, the number of cell on ICs increases dramatically. Power consumption has become one of the most important issues in a design theme. The method of using lower supply voltage to reduce power dissipation is a recent trend, but this technique has not been combined with the development in the physical design. In this paper we research the relation between placement and voltage scaling technique. There are three major phases in this algorithm. In the first phase, we develop a timing driven placer and a basic force directed placer. We place standard cells to its force-balanced position by using forced directed algorithm. And then according to the relative position of cells, we place cells until each cell is not overlapped to another. The second phase is voltage scaling phase. In this phase, we use the method “partition based voltage scaling” [2]. We add a new cost which is the distance between high voltage supply and gate into the gain of this method. The third phase is to create voltage rows and fix timing violation. We create high and low voltage rows according to the position of high and voltage cells, and then we move cells to the corresponding rows. After moving cells, if timing is incorrect, we fix the timing by gate sizing to guarantee that the timing is correct. In comparison with the power consumption of the circuit after placement, on average, our algorithm reduces the power consumption of the basic force directed placement by 45.1%, the power consumption of the timing placement by 45.6%, and the power consumption of commercial tool Placement(Cadence/SOC Encounter) by 36.7%.

參考文獻


[1] N. R. Quinn, “The Placement Problem as Viewed from The Physics of Classical Mechanics”, Design Automation Conference, 1975,
[2] H. H. Lee, S. H. Tsai, J. C. Chi and M. C. Chi, “A Partition-Based Voltage Scaling Algorithm Using Dual Supply Voltage for Low Power Designs”, International Symposium on VLSI Design, Automation &
[3] J. N. Kozhaya and L. A. Bakir, “An Electrically Robust Method for Placing Power Gating Switches in Voltage Islands”, Custom
[4] G. Holt and A. Tyagi, ”GEEP:A Low Power Genetic Algorithm Layout System”, IEEE Midwest Symposium, 1996, pp.
[5] Y. H. Huang and M. C. Chi, “Low-Power Driven Standard-Cell Placement Based on a Multilevel Force-Directed Algorithm”, SOC

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