新型電荷幫浦電路設計

The Design of New Charge Pump Circuits

林庚昱(Geng-Yu Lin)

指導教授 ： 黃文昌

崑山科技大學/工程學院/電子工程研究所/碩士(2009年)

摘要

在本論文中，我們提出四個新設計的電荷幫浦電路。在這些電路中，共 同的特點就是皆使用倍壓電路。前兩個電路是利用串接的倍壓脈波產生器而得到隨著級數而升高的脈波電壓輸出，並將此輸出時脈提供給多級相連接的MOS二極體及電容氣之組合，而在本研究中所使用的MOS二極體為PMOSFET所製作以降低其基底效應。而第一、二個電路之差別在於倍壓脈波產生器所供應的時脈分別是一級的時脈對應一級的電荷傳輸電晶體，以及一級的時脈對應兩級的電荷傳輸電晶體之差別。在後兩個電路中，是藉由倍壓電路和一組互平行的動態反向器所構成之傳輸電晶體電荷幫浦電路。第三個電路中所使用的傳輸電晶體為nMOS和pMOS交替使用，而第四個電路的傳輸電晶體皆為pMOS，目的是要消除基底效應，以增加輸出電壓值。前兩個電路藉由HSpice TSMC 0.35μm之製程模擬，在第七級的輸出電壓分別40.6V和60.3V。後兩個電路藉由HSpice TSMC 0.18μm之製程模擬，第五級的輸出電壓分別9.6V和10.3V。其中第四個電路亦藉由TSMC 0.35μm Mixed-Signal 製程來實現IC 晶片，此晶片大小為0.8877 × 0.7244 (mm2)，其電路消耗功率為1.6mW。

關鍵字

電荷幫浦

並列摘要

There are four kind of new charge pump circuits are present in the thesis. The basic circuit of these charge pump schemes is the voltage-doubler. A serial of MOS-diode with capacitor to be the charge transfer element and by using a chain of voltage-doubler which producing an increased output clock voltage as the stages of the chain was increased as the clock were designed in the first two circuits. For the reducing the body effect on the threshold voltage drop, the pMOS-diode was used. The main difference of these two circuits is that one stage of clock output provides one stage or two stages of the charge transfer diode, respectively. The latter two circuits were designed by combined a voltage-doubler with a set of paralleled dynamic inverter. Both nMOS and pMOS are used to be the charge transfer transistors in alternative in the third circuit. For the reducing of body effect, all the charge transfer transistors are designed by using pMOS in the fourth circuit. The first two circuits were simulated by HSpice with the model of TSMC 0.35?慆 process. It shows the pumping voltage of 40.6V and 60.3V after seven stage’s pumping, respectively. The latter two ircuits were simulated by HSpice with the model of TSMC 0.18?慆 process. It shows the pumping voltage of 9.6V and 10.3V after five stage’s pumping, respectively. The fourth circuit was also realized on chip by using TSMC 0.35?慆 mixed signal process. The chip area is 0.8877 x 0.7244 mm2 and the power consumption id 1.6mW.

並列關鍵字

Charge pump

參考文獻

[14]劉柏志,”高電壓電荷幫浦之設計與分析”,碩士論文,崑山科技大學,2007

[2]K.Naruke,S.Yamada,E.Obi,S.Taguchi,and M.Wada,”A NEW FLASH-ERASE EEPROM CELL WITH A SIDEWALL SELECT-GATE ON ITS SOURCE SIDE ” , IEEE J.Solid-State Circuits ,Dec. 1989

[3] J.Van Houdt ,L.Haspeslagh,D.Wellekens, L.Deferm, G.Groeseneken, H.E.Maes, “HIMOS-A High Efficiency Flash E2PROM Cell for Embedded Memory Applications”, IEEE J.Solid-State Circuits ,Dec. 1993

[6] J.F,Dickson,” On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique”,IEEE J.Solid-State Circuits, Vol. 11,June 1976, PP.374 – 378

[7] Wu J. T., Chang, K. L., “MOS Charge Pumps for Low-Voltage Operation”, IEEE J. Solid State Circuits, vol. 33, No. 4, April 1998, pp. 592-597.