本論文完成一套被動式影像自動對焦系統,以系統可程式化晶片(System-On-a-Programmable-Chip, SOPC)的架構,實現於可程式化邏輯閘陣列(Field-Programmable-Gate-Array, FPGA)開發平台。以FPGA晶片內部所建立的32位元處理器作為系統控制核心,並藉由硬體化的馬達運動控制模組與影像處理模組達到自動對焦的目的,同時藉由模組化的設計,提高系統在開發與移植上的彈性。 馬達控制迴路包含位置控制與速度控制,分別採用PD(比例-微分)控制器與PI(比例-積分)控制器。另外,實現CSDT(Constant Sample-time Digital Tachometer)估測法作為馬達的轉速量測,並且選用影像差距係數總合(Sum-modulus-difference, SMD)演算法作為影像清晰度的計算方法。系統採用執行二次全域搜尋法的方式作為進行一次對焦的焦點搜尋策略。 本論文的最後,將採用三種不同樣版的物體進行實際的對焦測試,以驗證此系統的可行性,並且比較以軟體實現SMD與硬體化SMD模組,兩者在效能上的表現差異。
This study used a System-On-Programming-Chip (SOPC) method and a development platform with a Field-Programmable-Gate-Array (FPGA) to develop a passive automatic focus control system. A 32-bit processor was established as the system control center within the FPGA, with hardware modules for control the motor movement and for processing images to achieve autofocus, In addition, the modularity of the design improved the flexibility of the system during development and porting. The motor control loop contained Proportional-Derivative (PD) and Proportional -Integral (PI) controllers for controlling position and speed, respectively. In addition, the Constant Sample-time Digital Tachometer (CSDT) method was used for measuring the motor speed, with the Sum Modulus Difference (SMD) algorithm being employed to calculate the image sharpness. System used twice global search methods as focus strategy. Finally, we tested three versions of an object to verify the feasibility of the system, thus determining any performance disparity between the SMD software and hardware modules.