使用I射線步進機的雙重圖形曝光技術以及其應用在元件製作之研究

A Study on Double Patterning Technique with i-line Stepper and Its Application to Device Fabrication

謝瑞桀(Rei-Jay Hsieh)

指導教授 ： 林鴻志 ； 黃調元

國立交通大學/電機學院/電子工程系所/碩士(2009年)

https://doi.org/10.6842/NCTU.2009.00912

摘要

在本論文中，我們發展出一種新穎的技術可利用Ｉ射線(I-line)光學步進機來製作次世代小於100奈米的閘極圖形，並應用其來製作元件。這技術包含了兩次光學微影以及後續製程。因為它不會受到如同一般製程中的繞射效應，其複雜製程帶來的好處是突破一般Ｉ射線光學微影方法的解析度極限(~0.3m)。這技術的解析度在本論文中已被證實可進展到約80奈米左右。數種非對稱源極/汲極元件在本論文中也用此技術來製作與分析，如穿隧式場效電晶體(TFET)以及非對稱式沿展之N型場效電晶體。

關鍵字

雙重微影技術 ； 微縮 ； 非對稱式電晶體 ； 穿隧式電晶體

並列摘要

In this thesis, we have developed a novel double patterning technique utilizing an i-line stepper for the formation of sub-100nm gate patterns and implemented this technique to the fabrication of devices. This technique consists of 2-step lithography and following etch process to form the gate patterns. Reward for the complicated process steps is the shrinkage of resulted patterns beyond the resolution limit of the conventional i-line lithographic method (~0.3m), since this technique doesn’t suffer the diffraction effect encountered in conventional process. Resolution capability of this technique has been confirmed to improve at least to 80nm in this thesis. Several types of devices with asymmetrical source/drain structure, such as tunneling field-effect transistors (TFETs) and n-MOSFETs with asymmetric extensions, were fabricated with this technique and characterized in this thesis.

並列關鍵字

double patterning ； scaling ； asymmetric MOSFET ； TFET

參考文獻

1. P. K. Bondyopadhyay, ”Moore’s law governs the silicon revolution,” IEEE Trans. Electron Dev., vol.86, pp. 78-91, Jan 1998.

3. S. Banerjee, W. Richardson, J. Coleman and A. Chatterjee, “A new three-terminal tunnel device,” IEEE Elec. Dev. Lett., vol.8, pp. 347-349, 1987.

4. Toshio Baba, ”Proposal for surface tunnel transistors,” Jpn. J. Appl. Phys., vol.31 , pp. 455-457, 1992.

5. William M. Reddick and Gehan A. J. Amaratunga, “Surface tunnel transistor,” Appl. Phys. Lett., vol.67, no.4, pp. 494-496, July 1995.

6. Zhang Q, Zhao W, Seabaugh A, “Low-subthreshold-swing tunnel transistors,” IEEE Electron Device Lett., vol.27, pp. 297-300, 2006.