透過您的圖書館登入
IP:18.225.149.32
  • 學位論文

金屬閘高介電n型金氧半場效電晶體及鰭式電晶體閘極電子穿隧電流的精確模擬

Accurate Modeling of Gate Electron Tunneling Current in Metal-Gate/High-K nMOSFET and nFinFET

指導教授 : 陳明哲

摘要


高介電質絕緣層可以抑制閘極漏電流而鰭式金氧半電晶體結構可以改善短通道效應的影響。藉由WKB近似理論建立的閘極穿隧電流已經被發表了。在本篇論文中,將會說明電子通過雙閘極元件中高介電質絕緣層的穿隧模型,而且將此模型應用到n型鰭式金氧半電晶體中。由於元件從單個閘極變成多閘極的結構,電子在各個能帶中擁有的能量公式需要被修正。藉由改變曲線擬合因數,修正後應用於雙層閘集結構的模型對於不同基底厚度依然成立。將滿足修正變數線性方程式中的基底厚度改變,只要知道基底厚度,修正變數就能夠被確定。 除了閘極電容電壓及閘極電流電壓的資料曲線擬合外,量測元件中的相關材料係數可以由進一步的對閘極電流取對數的曲線擬合得到更為正確的結果。由於高介電值層和介面層的介電係數差太大,平緩的過度漸層介於此兩層中加入,能改善對於在高電場中電流的曲線擬合。 由這幾個修正,測量的資料和模擬數據電流可以吻合。這可以更加了解電子在鰭式金氧半電晶體中的穿隧機制。

並列摘要


High-K stacks can suppress the gate leakage current while a FinFET structure has benefits of improving the short channel effects. Gate tunneling current model has been established based on WKB approximation. In this thesis, an electron tunneling model through high-K stacks will be constructed for double-gate devices, especially n-type FinFET. The electron subband energy should be modified for the change of the structure from single gate to multiple gates. This model established for double gate structure is also valid for different body thicknesses through different fitting factors used. A linear relation is obtained between body thickness and the subband fitting factor. Once the body thickness is known, the fitting factors can be determined accordingly. Material parameters of the experimental devices can be accurately determined by a new fitting of dln(Ig)/dVg-Vg in combination with the conventional Cg-Vg and Ig-Vg fittings. A gradual transition layer between high-K layer and interfacial layer can improve the fitting quality at high gate voltages owing to the large difference of permittivity between high-K dielectric and interfacial layer. With these modifications incorporated, good agreements with measured gate tunneling current can be achieved.The new model can also lead us to a better understanding of the gate tunneling mechanism in FinFET.

參考文獻


[ 2 ] Leonard F. Register, Elyse Rosenbaum, and Kevin Yang, “Analytic model for direct tunneling current in polycrystalline silicon-gate metal-oxide-semi- conductor devices,” Appl. Phys. Lett., vol. 74, no. 3, pp. 457-459, Jan. 1999.
[ 3 ] Kuo-Nan Yang, Huan-Tsung Huang, Ming-Chin Chang, Che-Min Chu, Yuh-Shu Chen, Ming-Jer Chen, Yeou-Ming Lin, Mo-Chiun Yu, Simon M. Jang, Douglas C. H. Yu, and M. S. Liang, “A physical model for hole direct tunneling current in p+ poly-gate PMOSFETs with ultrathin gate oxides,” IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2161-2166, Nov. 2000.
[ 4 ] Yijie Zhao and Marvin H. White, “Modeling of direct tunneling current through interfacial oxide and high-K gate stacks,” Solid-State Electronics, vol.48, no. 10-11, pp. 1801-1807, Dec. 2003.
[ 5 ] Saibal Mukhopadhyay, Keunwoo Kim, Ching Te Chuang, and Kaushik Roy, “Modeling and Analysis of Leakage Currents in Double-Gate Technologies,” IEEE Trans. Computer–Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 2052-2061, Oct. 2006.
[ 6 ] Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rjiv V. Joshi, Ching-Te Chuang, and Kaushik Roy, “Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50 nm double gate devices,” Microelectronics Journal, vol. 38, no. 8-9, pp. 931-941, Jan. 2006.

延伸閱讀