在多核心嵌入式平台使用平行處理加速H.264視訊解碼

Parallelization of H.264 video decoder for Embedded Multicore Processor

陳彥廷(Yan-Ting Chen)

指導教授 ： 蔡淳仁

國立交通大學/資訊學院/資訊科學與工程研究所/碩士(2014年)

https://doi.org/10.6842/NCTU.2014.00608

摘要

本論文主旨在於在多核心平台上對Baseline H.264/AVC decoder用不同的平行化方式達到加速的效果，並分析data parallelism與task parallelism的平行技術，如static scheduling與dynamic scheduling、static partition與dynamic partition、task buffer monitoring等等，並探討平行化過程中所產生的負擔與問題，如資料的搬移、記憶體使用率、synchronization、load balancing議題等等，以上的平行視訊解碼設計及分析是在一個新的應用處理器架構上進行[14]。這個新的多核心處理器架構可以在不增加額外system bus負擔下，採用工作切割精細的software-pipeline平行化方式，來增加pipeline-based video decoder的效能，根據我們實驗的結果，採用dynamic pipeline partition在三顆核心下能相對於單核心H.264/AVC解碼器有接近三倍的加速。

關鍵字

H264

並列摘要

In this thesis, we present two parallel decoding approaches to enhance the performance of H.264/AVC decoders on multiprocessor platform. We analyze data-level parallelism and task-level parallelism for various parallel decoding techniques, such as static and dynamic scheduling, static and dynamic partitioning or FIFO task buffers monitoring etc. We discuss some overheads and problems resulted from the parallelization process, such as data transfer, memory usage, synchronization, or load balancing issue etc. The investigation of parallel video decoding is conducted on a new multicore application processor architecture that facilitates the adoption of the fine-granularity software-pipeline parallelism without causing extra burden on the system bus and it will increase pipeline-based video decoder performance. Experimental results show that the adoption of the dynamic pipeline partition approach could nearly be three times faster than a single-core H.264/AVC decoder does.

並列關鍵字

H264

參考文獻

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