使用定位同步技術之非同步電路自動化流程設計

An Automatic Desynchronization Flow with Pinning Source-Synchronization

蔡廷南(Ting-Nan Tsai)

指導教授 ： 江蕙如

國立交通大學/電機學院/電子工程系所/碩士(2014年)

https://doi.org/10.6842/NCTU.2014.00610

摘要

近年來，因為在傳統的同步式電路(synchronous circuit)中，尤其是隨著製程往前推進，時脈相關的問題變的逐漸嚴重且難以處理、功耗也成為IC表現的一大限制，非同步式電路(asynchronous circuit)相關的研究逐漸的變得熱門。非同步式電路一方面不用處理時脈的合成和時差等問題，另一方面由於其運作之原理是每個資料路徑各自判定截取資料的時間，使得非同步電路的時序表現天生會比受到最糟路徑限制住時序週期的同步電路還好。對於雙軌式(dual rail)的非同步式設計而言，如何保持資料路徑跟控制路徑之間的時間關係正確是很重要的議題。
本論文首先提出了可以將一個同步電路非同步化(Desynchronization)從合成一路到後段繞線完成為止的一個完整的流程。接著在此流程中，我們提出了定位同步技術(pinning source synchronization)，藉以於佈局階段有效維持雙軌的時間關係較不受繞線以及之後的物理環境變化(PVT variation)波及。最後我們也討論例如部份非同步化等技術的可能效用。

關鍵字

非同步電路自動化流程 ； 定位同步技術

並列摘要

Recently, asynchronous design has become more popular to conquer the issues of clock synthesis and the power consumption in the traditional synchronous design. For dual rail protocol of asynchronous design, how to maintain the timing relation between the data line and the corresponding control line is a crucial issue. In this thesis, we propose pinning source synchronization to maintain the timing relation. We also present a framework that automatically transforms a synchronous design to an asynchronous design from RTL to layout. Moreover, our method can be easily extended to partial desynchronization, which can reduce some overhead while keeping the advantage of asynchronous design.

並列關鍵字

pinning source synchronization ； desynchronization

參考文獻

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