使用低壓元件堆疊來達成高壓積體電路之靜電放電防護設計

Stacks of Low-Voltage Devices for ESD Protection in High-Voltage Applications

湯凱能(Kai-Neng Tang)

指導教授 ： 柯明道

國立交通大學/電機學院/電子工程系所/碩士(2014年)

https://doi.org/10.6842/NCTU.2014.00940

摘要

在現今的電子產品中，許多積體電路都是使用高壓相關製程的，例如各式平板的驅動IC，電源管理IC，車用IC等。在高壓製程中，高壓電晶體往往具有比較複雜的結構，來撐高崩潰電壓，增加可操作的電壓區間，這也使得靜電放電保護的設計，更加有挑戰性。
在高壓的靜電放電防護設計中，常會使用橫向擴散電晶體(lateral diffused MOS, LDMOS)，也就是常見的高壓電晶體，與低壓電晶體相比，在同樣的布局大小下，通常高壓靜電保護元件的靜電耐受度表現較差，所以使用高壓保護元件，都要撐大元件大小，並且注意均勻導通度，以達到要求的靜電耐受能力。
在高壓靜電放電防護設計中，持有電壓(holding voltage)是一個重要的考量，當在靜電保護元件的持有電壓低於供給的電壓時，在應用上有可能會發生閂鎖效應(latchup)，在一些雜訊很多的環境中，這一點更是重要的考量。
相對於高壓靜電保護元件，低壓的靜電保護元件，往往都是充分驗證，而且有許多可行的方法增進其靜電耐受度，導通速度，導通均勻度。低壓的靜電保護元件，在單位面積下，靜電耐受能力很好。使用堆疊方法使整體的導通與持有電壓往上疊加，使它滿足高壓積體電路的需求，在面積與靜電耐受度的考量下，尋找最佳的方法。
在此篇論文中，實驗並驗證堆疊結構，並討論他們的問題以及改善方法，以及在不同形狀堆疊的情形。探討在堆疊中，擺放不同的元件，使其導通速度增加的方法。

關鍵字

靜電放電防護 ； 低壓元件堆疊

並列摘要

Nowadays, many integrated circuits (ICs) of electrical products are fabricated in a high-voltage process. For example, driver ICs for various display panels, power management ICs and automotive ICs are commonly fabricated in a HV process. In a high-voltage process, HV transistors are born with complicated structure for the increase of the operating range and breakdown voltage, and that makes electrostatic discharge (ESD) protection design more difficult and challenging.
In ESD protection design for HV applications, it is common to use lateral diffused MOS (LDMOS) as an ESD protection device. LDMOS is a general HV MOS, and its ESD robustness is worse than a low-voltage device’s. It has to enlarge LDMOS, and be aware of uniformity for ESD protection.
In ESD protection design for HV applications, holding voltage of a device is an important factor. When holding voltage of a device is lower than supply voltage, it is possible that latchup occurs in applications. In some noisy environment, this factor should be paid more attention.
Low-voltage devices are proved for good ESD robustness per area, and the devices can be enhanced by many methods. Stacking makes the devices’ trigger voltage and holding voltage increase so that the devices meet the conditions for HV applications. For area and ESD robustness concerns, stacking can be one of the best ways.
In this thesis, stacks for ESD protection are implemented and verified, and it is discussed for the problems and improvement. Stacked configuration in different shapes is also examined. Increasing turn-on speed by replacing with other devices will be discussed.

並列關鍵字

ESD protection ； Stacks of low-voltage devices

參考文獻

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