長距庫倫作用於塊材矽之探討

在摩爾定律的驅動下，在過去這幾十年來，金氧半場效電晶體的通道長度已被快速的微縮至奈米尺度，並且在接下來這幾年將邁入五奈米製程節點。在這樣的情況下，在汲極與源極產生之電位擾動將滲入通道之中，進而降低元件效能表現。為了清楚明白其物理圖像，了解潛藏於半導體中之機制雖是基本但是必要的。因此我們將聚焦於兩個有名的實驗觀點，一為能隙窄化，二為電子遷移率。在此論文中，我們首先藉由被強化的少數載子注入實驗數據來萃取電位擾動之大小，而此實驗數據在過去常被解釋為能隙窄化之結果。透過理論之計算，電漿被驗證為電位擾動之主要來源。我們進而將萃取得之電位擾動考慮進遷移率之微觀計算中，計算結果可重現實驗之數據。在電位擾動存在之區域，電子與電漿子之間的作用是相當重要的且需要被認真看待的。其對應之散射公式已被發表於文獻之中，但是相當複雜且不容易被理解。在最後，我們也提出一具有物理意義之模型做為另一選擇來解決這樣的問題，此模型相對簡單也可以彈性地被延伸。

關鍵字

電漿子；電位擾動；能隙窄化；遷移率

並列摘要

Driven by Moore’s law, the channel length of silicon MOSFETs has been aggressively scaled to nanometer region in the past decades, and will enter 5-nm technology node in the next years. In this situation, the generated potential fluctuations in the highly-doped source and drain regions will penetrate into channel and deteriorate the device performance. To make the physical picture clear, figuring out the underlying mechanisms at the semiconductor level is fundamental and crucial. Thus we focus on two well-known experimental points for the bulk silicon. One is the apparent bandgap narrowing, and another is the electron mobility in n-type silicon. In this thesis, we first extract the magnitudes of potential fluctuations in the heavily doped region via the experimental data of enhanced minority-carrier injection which has been explained by the apparent bandgap narrowing in the past. Through the theoretical calculations, the plasmon is verified as the main origin of potential fluctuations. Then we further conduct the microscopic mobility calculations with the extracted potential fluctuations taken into account. The calculated results can reproduce the experimental data well. For the regions with potential fluctuations, electron-plasmon interactions are important and need to be taken seriously. The scattering formalism has been published in the literature, which is quite complicated and not easy to understand. In the end, we also propose physical based model as the alternative way to deal with such problem. The model is much simple, making the extension flexible.

並列關鍵字

plasmons ； potential fluctuations ； bandgap narrowing ； mobility

參考文獻

[1] S. E. Thompson, et al., “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1790-1797, Nov. 2004.

[2] K. Mistry, et al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” in IEDM Tech. Dig., 2007, pp. 247-250.

[3] D. James, “Intel Ivy Bridge unveiled — The first commercial tri-gate, high-k, metal-gate CPU,” IEEE CICC, 2012, pp. 1-4.

[4] (2013). International Technology Roadmap for Semiconductors (ITRS) (ITRS 2013 Edition) [Online]. Available: http://www.itrs.net

[6] Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber, “High performance silicon nanowire field effect transistors,” Nano Lett., vol. 3, no. 2, pp.149 -152, Jan. 2003.

國際替代計量

長距庫倫作用於塊材矽之探討

全文下載

主題瀏覽