多目標演化法暨多準位訊號驅動方式在資通訊和生醫面板顯示器閘級驅動電路設計最佳化之研究

在資通訊產業中，一般面板顯示器被應用在許多方面，包括電視、手機、平板、醫學用的參數顯示器和超聲波醫療儀器顯示等方面，在顯示器中，面板建構在背光片上，且內部是由兩片偏光片所夾著，依序為主動式矩陣其中閘極驅動線為非晶矽閘極驅動電路所控制、液晶、透明電極和彩色濾光片。目前各尺寸的面板顯示器已被廣泛使用，為了製造更具高性能與高競爭力的面板顯示器，非晶矽閘極驅動電路設計的好壞扮演關鍵技術之一。傳統上，閘極驅動電路的設計是由有經驗的工程師進行手動調整與反覆測試，但隨著資通訊暨生醫面板顯示器需求的多樣化，閘極驅動電路的設計日漸複雜，需考慮的工程參數變多(數十個參數需要同時最佳化)；因此，基因演算法常被用來進行電路設計，但是基因演算法需要將多個設計規格寫成一個單一成本函數，對於閘極驅動電路同時需要滿足多個特性來說，其成本函數調整相當困難。最近發展的多目標演算法可以同時最佳化多個成本函數，成為電路設計最佳化可行且熱門的方向之一。本研究運用多目標演算法來最佳化非晶矽閘極驅動電路，同時針對中、大尺寸面板顯示器提出可以改善功率消耗的多準位驅動方式，所設計出來的閘極驅動電路與我國面板顯示器大廠合作，進行樣品製作與特性量測，並獲得很好的成果。首先，閘極驅動電路最佳化問題，依循實驗室開發的統合性優化平台可分為電路問題與最佳化計算方法兩部分。電路問題的主檔案會呼叫電路遮蓋檔與參數檔，分別提供參數位置與變動範圍，且主檔案提供最佳化需要的參數設定給C++連結程式；最佳化計算部分則由C++連結程式去利用多目標演算法在統合性優化平台上進行解的演化與挑選，並呼叫外部電路模擬器計算閘極驅動電路的特性至主檔案輸出資料文件，而最佳化停止條件是根據主檔案中設定的演化代數。我們利用此多目標最佳化方法進行六級串接在一起的閘極驅動電路設計，其每一級的閘極驅動電路有17顆電晶體以及4顆電容，考慮的目標規格為下降時間小於3微秒與漣波峰值小於-9伏特，原始設計的規格其下降時間為4.78微秒與漣波峰值為-8.81伏特，經由本研究的最佳化後，下降時間由4.78微秒減少到2.65微秒，且漣波峰值由-8.81伏特改善到-9.07伏特，並加入新的三階層驅動訊號到最佳化後的閘極驅動電路，結果顯示功率消耗減少，並且下降時間由2.65微秒進一步減少到2.35微秒，而漣波峰值由-9.07伏特降到-9.96伏特，整體來看，下降時間大幅度改善約50%，此外，此實作樣本量測的下降時間為2.48微秒和連波峰值為-11.3伏特，與模擬相符，並有更穩定的漣波。此外，應力效應會影響產品的穩定性和使用壽命，產生應力效應的主要因素有溫度、偏壓大小與持續導通時間長度等，每一顆薄膜電晶體導通時都會受到高電壓影響而產生臨界電壓偏移，因此，電晶體的導通時間相對於操作週期越短越好，在第四章中，我們所使用的電路為三個訊號驅動，工作週期為33%；在第五章，我們利用多目標最佳化方法進行十二級串接在一起的閘極驅動電路設計，並使用四個訊號驅動，降低其工作週期為25%，以減少應力效應，其每一級的閘極驅動電路有13顆電晶體以及2顆電容，目標規格為上升時間小於4微秒、下降時間小於5.5微秒、漣波振幅小於1.2伏特、電晶體總寬度小於12000微米和訊號的等效電容值小於25微微法拉，經過最佳化後，上升時間從3.63微秒減少到3.29微秒，減少約9%、下降時間從5.96微秒減少到5.37，減少約10%、漣波振幅從1.23伏特下降到1.15伏特，減少約7%，而電晶體總寬度則是從13550微米縮減到11635微米，縮小約14%，此外，訊號的等效電容值從25.8微微法拉減少到21.87微微法拉，改善約15%。在本論文的寫作上，第一章介紹面板顯示器的背景、應用和文獻回顧。第二章說明非晶矽薄膜電晶體的製程步驟，與參數萃取模擬器，並介紹基本閘極驅動電路操作。第三章說明本研究實現的多目標演算法與統合性優化平台，並舉例說明程式與檔案結構。第四章利用多目標最佳化方法進行六級串接在一起的閘極驅動電路設計，其每一級的閘極驅動電路有17顆電晶體以及4顆電容，並加入新穎的驅動方式加以探討，與實際製作樣本進行量測。第五章利用多目標最佳化方法進行十二級串接在一起的閘極驅動電路設計，其每一級的閘極驅動電路有13顆電晶體以及2顆電容，其樣本正在製作中。第六章會將本論文做總結，並提出未來展望。總之，在本論文中，我們成功採用多目標最佳化方法設計六級串接在一起的閘極驅動電路設計，並且加入新穎的三階層驅動方式，以減少能源消耗，並優化了閘極驅動電路特性，使得電路的下降時間有效縮短50%，提高面板顯示器的對比度，漣波也較為平穩，提升面板顯示器的穩定度，重要的是，我們所設計出來的閘極驅動電路，有實際與國內顯示器大廠合作進行樣品製作，並且做特性量測以驗證研究方法的正確性與可行性。此外，我們增加目標，用多目標最佳化方法進行十二級串接在一起的閘極驅動電路設計，同時提高電路的特性，其中下降時間、電晶體總寬度和訊號的等效電容值都有效減少超過10%，此外上升時間與漣波振福亦有分別9%與7%的改善。本研究成果可以用於面板廠量產具高性能高競爭力的中大吋的面板產品，隨著閘極驅動電路需求的規格增加，電路會更加複雜，本研究中使用的多目標最佳化方式在未來可以繼續創新與討論，亦能藉由新穎的電路驅動方式設計達到改善效果。

關鍵字

非晶矽薄膜電晶體；閘極驅動電路；多目標演算法；最佳化；電路設計

並列摘要

In Information and Communication Technology (ICT), the panel display had been widely used in many applications, such as TVs, cell phones, flats, multi-parameter monitors, and ultrasound medical equipments. The structure of TFT-LCD has a backlight unit and a panel display is composed of the active matrix which has gate lines controlled by ASG driver circuits, liquid crystal (LC), the transparent electrode and the color filter (CF) film between two polarizer films. Nowadays, panel displays with various sizes are widely used. To fabricate panel displays with high performance and competitiveness, ASG driver circuits play one of key techniques. In general, ASG driver circuit designs strongly rely on adjusting and testing by experienced engineers. However, with the diverse needs for panel displays of information, communication, and biomedical science, designs of ASG driver circuits are getting more and more complex. Thus, we should consider more engineering parameters which need to be optimized at the same time. The genetic algorithm (GA) is usually used for circuit designs, which we can only write one cost function with many design specifications. However, due to many characteristics of ASG driver circuits, the adjusting of the cost function is very difficult. Recently, the multi-objective evolutionary algorithm (MOEA) which can optimize many cost functions at the same time has become more popular in circuit designs. In this study, we optimize the ASG driver circuits by using the MOEA. To improve the power consumption of panel display, we propose the multi-level clock driving method. Cooperating with display manufacturer in Taiwan, we successfully fabricate the sample of the optimized ASG driver circuit which has excellent characteristics. First, the problem of the ASG driver circuit on unified optimization framework can be seperated into two parts, the circuit problem and the solver. The configuration file of the circuit problem calls the mask file which provides the positions of masked parameters as well as the parameter file which sets the ranges of parameters. The configuration file also provides parameters to intermediate _file (written by C++ program) for optimization. The solver generates and chooses the solutions. Furthermore, it also calls the external circuit simulator to calculate the characteristics of ASG driver circuits. The terminal condition is according to generations setting by the configuration file. We design a six-stage ASG driver circuit by using optimized method based on the MOEA. Each stage of this ASG driver circuit has 17 a-Si:H TFTs and 4 capacitors. The objective specifications are the fall time < 3 s and the peak voltage of the ripple < -9 V. The fall time and the peak voltage of the ripple derived from the original design are 4.78 s and -8.81 V, respectively. After optimization, the fall time successfully decrease to 2.65 s, and the peak voltage of the ripple decrease to -9.07 V. Then, in order to reduce the power consumption, we add a novel 3-level clock driving to the optimized ASG driver circuit. The fall time further reduce to 2.35 _s and the peak voltage of the ripple reduce to -9.96 V. Overall, the fall time has about 50 % reduction. Moreover, the fall time of measured data is 2.48 s; the peak voltage of the ripple is -11.3 V. The measured data has a good agreement with the values of simulations, and the ripple of ASG driver circuit also become more smoother. In addition, stress effect would affect the stability and the lifetime of products. The factors of stress effect are temperature, the magnitude of bias voltages and the conducting time. Because of high level voltages, each TFT will suffer from the offset of the threshold voltage. Therefore, we hope the conducting time of TFT become shorter. In Chapter 4, we drive the ASG driver circuit by using three clock signals, and its duty ratio is 33%; in Chapter 5, we design a twelve-stage ASG driver circuit with four clock signals by using optimized method based on the MOEA, and successfully reduce the duty ratio to 25% which decreasing the stress effect. Each stage of the ASG driver circuit has 13 a-Si:H TFTs and 2 capacitors. The objective speci_cations are the rise time < 3.5 s, the fall time < 5.5 s, the amplitude of the ripple < 1.2 V, the total width of TFTs < 12000 m and the clock Ctotal < 25 pf. After optimization, the rise time successfully decrease from 3.63 s to 3.29 s (9% reduction), the fall time decrease from 5.96 s to 5.37 s (10% reduction), the amplitude of the ripple decrease from 1.23 V to 1.15 V (7% reduction), the total width of TFTs decrease from 13550 m to 11635 m (14% reduction), and the clock Ctotal decrease from 25.8 pf to 21.87 pf (15% reduction). In this thesis, Chapter 1 introduces the background, the applications of panel displays, and literature reviews. The process of a-Si:H TFT, the parameter extractor, and operations of the basic ASG driver circuit are shown in Chapter 2. Chapter 3 illustrates the multi-objective evolutionary algorithm as well as the unified optimization framework and give an example to explain the programs and file formation. In Chapter 4, we use the optimized method based on the MOEA to design a six-stage ASG driver circuit. Each stage of the ASG driver circuit has 17 a-Si:H TFTs and 4 capacitors. After that, we apply a novel multi-level clock driving to the optimized ASG driver circuit and fabricate the sample to be measured. In Chapter 5, we further design a twelve-stage ASG driver circuit by using the optimized method based on the MOEA. Each stage of the ASG driver circuit has 13 a-Si:H TFTs and 2 capacitors, and the sample of this ASG driver circuit is fabricating. Chapter 6 will conclude this study and give the future works. Overall, in this thesis, we have successfully designed a six-stage ASG driver circuit by using optimized method based on the MOEA. To improve the power consumption of panel display and characteristics of the ASG driver circuit, we have proposed the 3-level clock driving method. The fall time has about 50% reduction, and it can increase the contrast ratio of panel displays. Ripple become more smoother, and it can increase the stability of panel displays. The most important is we have fabricated the sample of optimized ASG driver circuit with the display manufacturer in Taiwan and the measured data also has a good agreement and feasibility with our researches. Moreover, we added more objectives, and designed a twelve-stage ASG driver circuit by using optimized method based on the MOEA. We have successfully improved all characteristics of the ASG driver circuit at the same time, such as amplitude of the fall time, the total width of TFTs and the clock Ctotal have over 10% reduction, the ripple has 7% reduction and the rise time also has 9% reduction. This study can apply to medium or large panel products with high performance and competitiveness. With the increasing of specification requirements, ASG driver circuit designs are getting more and more complex. Innovation of the optimized method based on the MOEA in this study can be continuously discussed in the future. The designed of the novel clock drivings is also one of key techniques to improve characteristics of ASG driver circuits.

並列關鍵字

a-Si:H TFTs ； gate driver circuit ； multi-objective evolutionary algorithm ； optimization ； circuit design

參考文獻

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多目標演化法暨多準位訊號驅動方式在資通訊和生醫面板顯示器閘級驅動電路設計最佳化之研究

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