晶粒尺寸於垂直閘極半導體-氧化矽-氮化矽-氧 化矽-半導體記憶體元件特性變異之研究

Effect of Grain Size on the Performance Variation of the Vertical Gate SONOS Memory Cell

盧立偉(Li-Wei Lu)

指導教授 ： 崔秉鉞

國立交通大學/電機學院/電子工程系所/碩士(2014年)

https://doi.org/10.6842/NCTU.2014.01051

摘要

在本論文中，我們製備不同晶粒尺寸的垂直閘極之快閃記憶體並且量測不同晶粒尺寸的元件，於初始狀態以及在Fowler-Nordheim 寫入與抹除機制中之差異。由於垂直閘極的元件，其通道是在側壁兩側且經過垂直方向的蝕刻，所以在探討晶粒邊界對於元件特性變異之影響時，不同元件表面的粗糙度的差異相較於平面型的元件來的小，因此可以更準確的幫助我們辨別晶粒邊界對於元件特性之影響。
在初始狀態的元件特性討論中，我們發現臨界電壓及次臨界擺幅的平均值隨通道中的晶粒邊界數量變少而變小。而在臨界電壓及次臨界擺幅的變異度上，我們發現兩者皆與通道中晶粒邊界的數量以及晶粒邊界缺陷密度的變異度大小有關。雷射退火的元件擁有較低的晶粒邊界缺陷密度變異，所以其導通電壓及次臨界擺幅變異度由晶粒邊界數量主導，隨著晶粒邊界數量變少，雷射退火的元件變異也變小且愈趨於單晶的元件。而熱退火的元件擁有較高的晶粒邊界缺陷密度變異，所以當晶粒邊界數量變少時，其元件特性由晶粒邊界邊界缺陷密度變異度主導，元件特性變易仍很大。
在Fowler-Nordheim 寫入速度比較中，不同的晶粒尺寸的元件，其寫入的速度也不同，當通道中晶粒數量越多，其寫入的速度也越快。其原因是晶粒邊界有大量的缺陷，在Fowler-Nordheim 寫入時，能量低於費米能階的電子將被晶粒邊界缺陷捕捉，使得該處的傳導帶產生位能障礙相較於沒有晶粒邊界的地方，有晶粒邊界經過的區域其表面的能帶彎曲比較小，而由於所加的閘極電壓處處相等，所以在晶粒邊界處會有較多的電位差落在穿隧氧化層，使得寫入的速度更快。
在Fowler-Nordheim寫入速度變異度比較中，我們發現Fowler-Nordheim寫入速度的變異度和晶粒邊界的數量無關，而與不同的通道退火方式進而得到不同的晶粒邊界缺陷密度的變異度有關係。相較於雷射退火，以熱退火的方式將得到較大的Fowler-Nordheim寫入速度變異度，所以我們推測，以熱退火的方式會得到比較大的晶粒邊界缺陷密度的變異度。
在Fowler-Nordheim 抹除速度比較中，我們發現不同的晶粒尺寸的元件之間的抹除速度並無明顯的差異。原因是在抹除機制中是將電洞注入氮化矽層內將其電子中和，而由於電洞的能障大於電子，因此通道中的晶粒邊界捕捉電洞使得在落在穿隧氧化層的電壓提高進而增強Fowler-Nordheim 抹除的速度的效應相對而言較不顯著。
在Fowler-Nordheim抹除速度變異度比較中，我們發現與Fowler-Nordheim寫入相同的趨勢，且變異度較小，其結論也間接驗證了上述的推論，由於電洞的能障大於電子，所以晶粒邊界效應對Fowler-Nordheim抹除機制相較起來較不顯著。

關鍵字

半導體-氧化矽-氮化矽-氧化矽-半導體 ； 晶粒邊界

並列摘要

In this work, we fabricated the vertical gate thin film transistor SONOS (VG TFT SONOS) devices with different channel grain sizes and study the grain boundary effect on IV characteristic in fresh state, Fowler-Nordeim (FN) program speed, FN program state variation, FN erase speed and FN erase state variation. Compared with planer TFT SONOS devices, the channel of VG TFT SONOS devices is fabricated at sidewall and etched during the active region pattern process. The surface of the etched sidewall of VG TFT SONOS devices is supposed to be smoother than the top surface of planer TFT SONOS devices. As a result, the VG TFT SONOS devices can help us study grain boundary effect more precisely and reduce the surface roughness issue.
In terms of basic IV characteristic in fresh state, grain boundary containing lots of electron trapping centers increases the surface potential and interface trap density which enlarges the threshold voltage (V_th) and degrades the subthreshold swing (S.S.). As a result, the mean value of V_th and S.S. decrease when the number of grain boundary decreases. Furthermore, the V_th and S.S. variation are related to the number of grain and the grain boundary trap density variation. Because laser annealed poly-Si devices contain lower grain boundary trap density variation, the V_th and S.S variation are dominated by the number of grain. When the number of grain decreases, the V_th and S.S variation of laser annealed poly-Si devices decrease and get close to that of single crystal devices. However, with large grain boundary orientation variation which results in large grain boundary trap density variation, thermal annealed poly-Si devices still exhibit large V_th and S.S variation when the number of grain decreases.
For FN program speed comparison, devices with different grain sizes have different program speed. According to our measurement, the program speed is enhanced when the number of grain boundary increases. It is because grain boundary will increase interface trap density and those electrons whose energy are below Fermi-level will be trapped and create energy barrier at conduction band. During FN program, with applied gate bias, more grain boundary traps will be filled with electrons. As a result, those regions with grain boundary have smaller band bending than other regions. Because gate bias is the same whether there are grain boundaries or not, larger gate voltage will drop on the tunneling oxide at grain boundaries so that the program speed is enhanced. In other word, when the number of grain boundary increases, the program speed also increases.
For FN program state variation, we find that the FN program state variation is less to do with the number of grain boundary. It is the grain boundary trap density variation among samples that dominates the program state variation. According to the measurement results, we conclude that the furnace annealed sample has the largest grain boundary trap density variation than the laser annealed sample and the single crystal sample.
For FN erase speed comparison, there is no apparent difference among different grain size devices. It is because the barrier of hole is larger than electron. As a result, the grain boundary effect on FN erase is not as apparent as that of the FN program.
For FN erase state variation comparison, we find that the FN erase state variation shows smaller and similar tendency with that of FN program state which responds to the aforementioned deduction. In conclusion, Grain boundary effect is more significant on the FN program operation and less to do with the FN erase operation.

並列關鍵字

SONOS ； Grain boundary

參考文獻

[1]. D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” J. Bell Sys. Tech., vol.46, pp.1288, 1967.

[2]. A. Goda and K. Parat, “Scaling directions for 2D and 3D NAND cells,” in IEDM Tech. Dig., pp. 2.1.1, 2012.

[3]. K. Parat "Recent developments in nand Flash scaling", in Symp. VLSI Tech. Dig., pp. 101, 2009.

[5]. S. Lai, H. Lue, J. Hsieh, M. Yang, Y. Chiou, C. Wu, T. Wu, G. Luo, C. Chien, E. Lai, K. Hsieh, R. Liu, and C. Lu, “Study of the Erase Mechanism of MANOS (Metal/Al2O3/SiN/SiO2/Si) Device,” IEEE Electron Device Lett., vol.28, no.7, pp. 643, 2007.

[6]. C. H. Lee et al., “A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memories,” in IEDM Tech. Dig., pp. 26.5.1, 2003.