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  • 學位論文

摻雜後活化對多晶矽穿隧式電晶體之影響

Effects of Dopant Activation on Poly-Silicon Tunnel Field-Effect Transistors

指導教授 : 趙天生

摘要


穿隧式場效電晶體具有較高的開關電流比、極低漏電流以及陡峭的次臨界擺幅,因此被認為在未來低功耗元件應用上,極具潛力。在本研究中,研究不同的摻雜後活化方式,對於多晶矽穿隧式場效電晶體的影響。 相較於利用600 ℃ 24小時的固相結晶法的穿隧式場效電晶體,以1000 ℃極快速熱退火的n-通道穿隧式場效電晶體,具有2.2倍高的導通電流,但稍微提高次臨界擺幅。在p-通道穿隧式場效電晶體方面,以900 ℃ 快速熱退火30秒的穿隧式場效電晶體,提高1.8倍的導通電流,但同樣增加了次臨界擺幅。藉由實驗發現,較高的活化程度會造成較高的導通電流,而次臨界擺幅與載子的擴散程度有極大的相依性。 另一方面,利用微波退火的方式來活化載子,不同於高溫活化,微波退火被視為低溫的活化方式,可以有效抑制載子的擴散。因此,利用微波退火活化的n-通道與p-通道穿隧式場效電晶體,展現出較高的開關電流比與較好的次臨界擺幅。此外,較低的門檻電壓表示利用微波活化的穿隧式場效電晶體,具有較高的穿隧機率與較小的擴散程度。從本篇研究中,我們發現微波退火在未來穿隧式電晶體的應用上,極具潛力。

並列摘要


Tunnel field-effect transistor (TFET) is considered as a promising candidate for future ultra-low power device. It has been known that TFET exhibits ultra-low leakage current, higher on/off current ratio and lower than 60 mV/dec subthreshold swing at room temperature. This study discusses the effect of activation on polycrystalline silicon (poly-Si) TFETs by utilizing different annealing conditions. Compared with TFET annealed by SPC at 600 ℃ for 24 hours, the n-channel TFET (NTFET) annealed by 1000 ℃ spike exhibits 2.2-fold higher on current but slight degradation of average subthreshold swing (S.S.ave). For p-channel TFET (PTFET), 900-℃ 30-sec PTFET has 1.8-fold higher on current but also sight degradation of S.S.ave. These experimental results demonstrate that the higher on current is due to higher amount of dopant activation and S.S. strongly depends on the extent of dopant diffusion. On the other hand, microwave annealing (MWA) is used to activate dopant. Unlike the high temperature activation, MWA is considered as low temperature annealing which can suppress dopant diffusion. Therefore, both type of TFETs annealed by MW shows higher on/off ratio and superior S.S.. The addition, the lower threshold voltage (Vth) of MW TFET indicates higher tunneling probability due to the smaller extent of dopant diffusion. From these result, we found that MWA has potential application in future TFET technology.

參考文獻


[1] C. H. Fa and T. T. Jew, "The Poly-Silicon Insulated-Gate Field-Effect Transistor," IEEE Trans. Electron Dev., vol. ED-13, pp. 290-291, 1966.
[2] T. J. King, "Trends in Polycrystalline-Silicon Thin-Film Transistor Technologies for AMLCDs," presented at the Proc. 2nd Int. Workshop AMLCDs, 1995.
[3] F. Hayashi and M. Kitakata, "A High Performance Polysilicon TFT Using RTA and Plasma Hydrogenation Applicable to Highly Stable SRAMs of 16 Mbit and Beyond," presented at the VLSI Symp. Tech. Dig., 1992.
[4] Y. Hayashi, H. Hayashi, M. Neyishi, T. Matsushita, M. Yagino, and T. Endo, "A Thermal Printer Head With Cmos Thin-film Transistors And Heating Elements Integrated On a Chip," in Proc. ISSCC Tech. Dig., 1988, p. 266.
[5] I. W. Wu, H. Tiao-Yuan, W. B. Jackson, A. G. Lewis, and A. Chiang, "Passivation Kinetics of Two Types of Defects in Polysilicon TFT by Plasma Hydrogenation," IEEE Electron Dev. Lett., vol. 12, pp. 181-183, 1991.

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