多源時脈網路合成之比較研究

A Comparative Study on Multisource Clock Network Synthesis

陳玟欣(Wen-Hsin Chen)

指導教授 ： 陳宏明

國立交通大學/電機學院/電子工程系所/碩士(2015年)

https://doi.org/10.6842/NCTU.2015.00863

摘要

混合時脈架構提供一個時脈樹及網格之間的折衷方案，其中大部分的相關研究都著重於樹驅動網格結構的最佳化，但我們對IC Compiler中一套流程的效果和改進感興趣，它稱作多源時脈樹合成：一個使用粗略網格結合多顆局部子樹的架構。因此，我們透過分析傳統時脈樹和多源時脈樹在一個實際工業用設計案件的結果品質來呈現此研究。我們同時也提出一些簡易直覺的方法來改善多源時脈樹的效能，尤其是針對減少時脈偏移的部分。根據實驗結果，我們指出每個方法的優缺點、提供如何設置適合一個設計的架構的建議，最後總結一些未來可鑽研的研究方向。

關鍵字

時脈分佈網路 ； 混合時脈架構 ； 多源時脈樹合成 ； 時脈網格 ； 不規則網格 ； 分節點決定

並列摘要

Hybrid clock architecture offers a compromise between tree and mesh. While most of the relative works focus on tree-driven-mesh configuration, we are interested in the performance and optimization of multisource CTS flow provided by IC Com-piler, which applies a coarse mesh with local sub-trees. Therefore, we analyze the QOR of conventional clock tree and multisource CTS on a real industrial design. We also propose several heuristic approaches to improving the performance of multisource CTS, especially for skew optimization. According to the experiment results, we reveal the benefits and drawbacks of each method, give some guidelines for determining the proper configuration for a design, and then summarize some future research directions.

並列關鍵字

clock distribution network ； hybrid clock architecture ； multisource CTS ； clock mesh ； non-uniform mesh ； tap point determination

參考文獻

[1] L. Xiao et al., "Local clock skew minimization using blockage-aware mixed tree-mesh clock network," Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., pp. 458-462, 2010.

[2] D. Bode et al., "QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration," Proc. Euromicro Conf. Digital System Design: Architectures, Methods and Tools, pp. 141-146, Sept. 2010.

[3] X.-W. Shih et al., "High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees," Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., pp. 452-457, 2010.

[4] C. Yeh et al., "Clock distribution architectures: A comparative study," Proc. 7th Int. Symp. Quality Electronic Design, pp. 85-91, 2006.

[5] A. Abdelhadi et al., "Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks," Integration, the VLSI Journal, vol. 46, pp. 382-391, Sept. 2013.