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  • 學位論文

使用空間相關性分析之雙級運算放大器佈局

Two-Stage OP-Amp Layout by Spatial Correlation Analysis

指導教授 : 陳竹一
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摘要


傳統在做電路模擬分析時,往往將元件參數彼此間的變動視為獨立而不相關,但是電路在晶圓廠製造過程中,電晶體彼此間的參數變動會有某種程度的關聯性;故本論文主要是建立一個:引入元件參數彼此間有空間相關性的模擬方式,來分析雙級運算放大器效能的表現,並藉由此方法來找尋類比電路在佈局時電晶體最佳的擺放位置。

並列摘要


We used to treat the parameter between devices as independent in traditional circuit simulation. However, the parameter variation in each transistor should have certain correlation during manufacturing process. This thesis presents a methodology to simulate a two-stage OP-Amplifier with spatial correlation in each transistor parameter. Based on this method, the best transistor permutation in this analog circuit is found.

參考文獻


[1] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid State Circuits, vol. 24, Page(s): 1433-1440, October 1989.
[2] Teresa Serrano-Gotarredona, Bernabe Linares-Barrabco, “Systematic CMOS Transistor Mismatch Characterization” Digital Object Identifier 10.1109/ISCAS.1996.541913, Vol. 4, Page(s): 113-116, May 1996.
[3] Teresa Serrano-Gotarredona, Bernabe Linares-Barrabco, “Cheap and Easy Systematic CMOS Transistor Mismatch Characterization” Digital Object Identifier 10.1109/ISCAS.1998.706977, Vol. 2, Page(s): 466-469, 31 May - 3 June 1998.
[4] Teresa Serrano-Gotarredona, Bernabe Linares-Barrabco, “A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation” Digital Object Identifier 10.1109/ISCAS.2000.858700, Vol. 4, Page(s): 109-112, 28-31 May 2000.
[5] Teresa Serrano-Gotarredona, Bernabe Linares-Barrabco, “A New Five-Parameter MOS Transistor Mismatch Model” IEEE Electron Device Letters, Vol. 21, No.1, Page(s): 37-39, January 2000.

被引用紀錄


陳保霖(2007)。電阻串數位類比轉換器之類比多工器設計〔碩士論文,國立中央大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0031-0207200917350659
邵桂裕(2008)。多通道LED驅動電路〔碩士論文,崑山科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0025-2208200810063800

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