DRAM中的被動式電壓對比

Passive Voltage Contrast in DRAM

王嘉鴻(Chia-Hung Wang)

指導教授 ： 劉正毓 ； 高振宏

國立中央大學/工學院/化學工程與材料工程學系/碩士(2007年)

摘要

被動式電壓對比 在半導體電路裡面為一種有效率及成功率高的檢測技術。可以運用在對於不同種類的電路缺陷，如 開路所造成的不正常高電阻，短路所造成的漏電流。 在電壓對比技術中，掃描式電子顯微鏡與聚焦離子束系統為主要運用儀器。由於電壓對比產生原理中，兩系統對於試片所造成的效果類似，可以在此論文中假設為相近的作用源。本文中，對於電壓對比的原理有粗略的提及。 而實驗中所觀察的試片為 華亞科技公司生產的 110nm製程 DRAM晶片。在對晶片的電壓對比觀察實驗中，選擇金屬線與金屬線中連結層為主要觀察部位。 文中對於各接觸層的電壓對比圖像，利用不同加速電壓所造成的顯示成果作討論。對於電子束與離子束所造成的差異，也有整理。

關鍵字

記憶體 ； 電壓對比

並列摘要

Passive voltage contrast was very successfully implemented in DRAM to identify the location different mechanisms of circuit failure, such as
failing continuity, high resistance, current leakage, and functionality.
Scanning Electron Microscope (SEM) and Focused Ion Beam (FIB) systems are routinely utilized for passive voltage contrast. The both SEM
and FIB system assume a general familiarity in this work; in addition,brief explanations of some basic concepts will be mentioned.
In this thesis, a background explanation of the passive voltage contrast (PVC) technique in both the SEM and FIB. 110nm Inotera DRAM chip
was used be observing sample.
Layer-by-layer deprocessing and top-view examinations were used to do the structure inspection at contact level prior to passive voltage contrast imaging. Several passive voltage contrast image examples of contact level are included to outline the technique and results of this study that variant voltage and beam source are discussed.

並列關鍵字

Voltage Contrast ； DRAM

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