一個寬頻鎖相迴路具有全域操作的高線性度壓控振盪器

近年來超大型積體電路蓬勃發展，電路的效能及速度也隨著製程技術的精進而提升，且目前的晶片皆趨向整合成單晶片系統(System-on-Chip)，所以在整合系統中各個子電路區塊常會出現操作的時脈相位不同，導致輸出資料出現錯誤，因此需要鎖相迴路(PLL) 來減少相位偏差，使得整合系統中各個子電路的時脈相位一致，減低輸出資料的錯誤，其中的關鍵在於降低鎖相迴路輸出訊號的抖動，可以藉由壓控振盪器(VCO)的高線性度與降低Kvco來達成此目標，本論文將致力於高線性度壓控振盪器的探討。本論文提出之寬頻鎖相迴路具有全域操作的高線性度壓控振盪器，從構想如何實現高線性度壓控振盪器開始，進而理論推導驗證高線性度壓控振盪器的特性式 f=Kvco•Vctrl+fmin 的正確性，其中的關鍵點在於壓控振盪器的偏壓電路，它的輸入電壓Vctrl與輸出電流Ictrl的關係必須是線性的，為此本論文提出四種符合線性要求的偏壓架構，分析其優劣好壞，從中挑選出的最佳偏壓架構，經過設計模擬確認，具有全域操作、寬頻、寬壓的優良特點，並以此為基礎建構出多頻段具有全域操作的高線性度壓控振盪器，最後實現本論文之鎖相迴路，可產生具有低抖動之五個相位的頻率，達到輸出訊號低抖動的效果，且在不同製程和溫度變化下， 80MHz~160MHz 的頻率範圍皆能正確鎖定。本論文以CIC CMOS 0.18um 1P6M 虛擬製程來實現，電路的工作電壓為1.8V，操作溫度範圍為0℃ ~ 75℃，鎖相迴路的輸入參考頻率範圍為5MHz~10MHz，輸出頻率範圍鎖定在80MHz~160MHz，鎖定時輸出時脈抖動量為19.2ps~18.1ps (pk-pk)。鎖定時間在 51.5us~49.1us，其消耗功率為 1.86mW~3.29mW。

關鍵字

寬頻；鎖相迴路；全域；線性度；振盪器

並列摘要

In recent years the performance and speed of VLSI circuits grew up with scale-down process, and now the chip changes to integrate SOC. There is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. The different phase of operate clock that caused to output data error in integrate system. Hence, it needs Phase-Locked Loop (PLL) for decreasing phase error that make the clock phase is corresponding in order to decrease output data error in sub-circuit of integrate system. The key point is to decrease the jitter of PLL output signal. The high linearity of Voltage-controlled Oscillator(VCO) achieves the goal. In this thesis, a wide band PLL with a high linearity voltage-controlled oscillator(HLVCO) in full range is proposed. How to achieve a HLVCO ? A idea is the beginning. Then validate the correctness of the HLVCO characteristics: f=KvcoVctrl+fmin by theoretic derivation. The key point is the performance of VCO bias circuit in the overall develop process. That is the relations of input voltage Vctrl and output current Ictrl of VCO bias have to be linear. In this thesis, four bias architectures achieving linear requirement are presented. First choose a best one from analyzing their advantages and drawbacks. Then from the process of design, simulation to validate the best one posses good features of full range operation, wide band and wide voltage. In the basis a multi-band HLVCO in full range operation is constructed. Finally a PLL is developed in this thesis. It produces five low jitter output phases achieving the goal of low output jitter mentioned previously. In the different process corners and temperatures the frequency range of 80MHz~160MHz is locked correctly. We use the CIC CMOS 0.18um 1P6M virtual process with supplying 1.8V voltage in proposed PLL. The temperature range is 0℃ ~ 75℃. The reference input frequency range is 5MHz~10MHz and the output frequency range is 80MHz~160MHz. The jitter of output frequency is 19.2ps~18.1ps (pk-pk). The lock time is 51.5us~49.1us and the power consumption is 1.86mW~3.29mW.

並列關鍵字

Wide Band ； PLL ； Linearity ； VCO ； Full Range

參考文獻

[5] Floyd M. Gardner, “Phaselock Techniques”, 2-th Ed., New York：Wiley & Sons,1979.

[17] S. Kim, K. Lee, Yong. Moon, D-K Jeong, Y.C., and H.K. Lim, “A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL,” IEEE Journal of Solid-State Circuit, vol. 32, pp. 691-700, May, 1997.

[1] T.H. Lin, and Y.J. Lai, “A 10-GHz CMOS PLL with an Agile VCO Calibration,” IEEE Asian Solid-State Circuits Conference, pp. 213-216 , 2005.

[2] F. M. Gardner, “Charge-pump phase-lock loops,”IEEE Trans. Commun. vol.28. pp.1849-1858,Nov. 1980.

[4] Rapinoja, T., Stadius, K., Halonen, K., “Behavioral Model based Simulation Methods for Charge-Pump PLL's,” Baltic Electronics Conference , pp.1– 4 ,Oct. 2006.

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一個寬頻鎖相迴路具有全域操作的高線性度壓控振盪器

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