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  • 學位論文

鉑矽化物於矽碳磊晶層上生成行為及其熱穩定性之探討

Effects of Platinum Silicide Formation on Si1-yCy Epitaxial Layers and Thermal Stability

指導教授 : 李勝偉
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摘要


在互補式金氧半電晶體元件尺寸日益縮小的趨勢下,自我對準金屬矽化物製程相關技術也日漸重要。近幾年來矽碳磊晶層被認為是未來極具潛力的汲極/源極材料,而要成功的整合矽碳磊晶層到標準元件製程流程裡,可靠的金半接觸對於矽碳磊晶層在汲極/源極的應用是必要的。鉑矽化物因具有較低的蕭基能障,可應用於蕭基電晶體上,但也同樣遇到熱穩定性較不佳的問題。因此,本研究嘗試使用矽碳磊晶層來改善鉑矽化物之熱穩定性,進一步探討鉑矽化物形成於矽碳磊晶層上之生成行為影響。研究發現鉑矽化物系統中有不可避免之原生氧化層存在,而鉑矽化物的生成必頇透過氧化層中的孔洞來進行反應。在有添加碳的系統中發現,碳原子不但降低PtSi相生成的速率也提高了鉑矽化物的熱穩定性。另外,添加碳也使PtSi較不易產生結塊的情形,同時也寬化了鉑矽化物的製程溫度窗。另一方面,有添加碳原子的試片即使經過長時間的退火其也均還保持相當良好的熱穩定性。 近幾年來,通道應變工程已成為最具潛力的技術。而其中,矽碳磊晶層之熱穩定的研究逐漸成為一研究的課題。因此,本研究中嘗試利用晶格應變技術分析矽碳磊晶層試片在經過退火過後其應變分佈的情況。研究發現矽碳磊晶層試片在剛開始退火階段其應變會增加,在退火800℃時矽碳磊晶層中碳原子濃度會增加0.1%,藉由應變晶格分析觀察到退火過後之矽碳磊晶層中應變強度愈靠近試片表面的地方愈大,推測是由於較慢成長之矽碳磊晶層中空孔較多使得位在間隙位置上的碳原子會佔據在取代位置上,導致碳原子濃度增加及應變的強度增加。另外當退火溫度再增高至900℃時應變會被釋放,推測是由於碳析出形成含有碳之間隙化合物所造成。

關鍵字

矽化物 矽碳磊晶層 熱穩定性

並列摘要


Strain engineering is commonly used for improving the performance of metal-oxide-semiconductor (MOS) devices. For example, n-channel MOS (NMOS) devices with silicon-carbon  (Si1-yCy) grown in the source and drain (S/D) regions as uniaxial compressive stressors for the channel can achieve significant drive current improvements. However, successfully integrating Si1-yCy epilayers into a standard device process flow requires reliable metal-silicide contacts in the Si1-yCy S/D regions. Pt silicide formed on p-type silicon has a low Schottky barrier height, which useful as Schottky transistors. However, Pt silicide has poor thermal stability. In this study, the reaction between Pt and Si1-yCy epilayers with an interfacial oxide layer was investigated. Pt silicide has inevitable oxide layer, which as a diffusion barrier layer. During the silicidation, Pt atoms diffused to react with Si through the oxide pinholes. C atoms play a critical role in Pt silicide microstructure and reaction. The presence of C atoms retards the growth kinetics of PtSi and significantly enhances the thermal stability of PtSi thin films. In addition, C atoms suppressed PtSi agglomeration and widened the process window of low-resistivity PtSi silicides. On the other hand, the thermal stability of Pt silicides in the Pt/Si1-yCy samples was found to be significantly improved, even after long-time annealing at 800 ℃.  In recently years, channel strain has been becoming a promise technique. Strain distribution with different depth of annealed Si1-yCy epilayers using lattice strain analysis were investigated in this study. At the initial stage of annealing, the strain of Si1-yCy epilayers increased. The Cs increased 0.001 in the Si1-y2Cy2 epilayers sample annealed at 800 ℃. Lattice strain analysis was performed using high-resolution transmission electron microscopy (HRTEM) and diffractograms obtained by fast Fourier transform of HRTEM images. The magnitude of compressive strain was larger towards Si1-y2Cy2 epilayers sample surface. It speculates that C atoms at interstitial sites were incorporated into substitutional sites after annealing, resulting in Cs and strain increment. In addition, no strain relief by the introduction of misfit dislocations was detectible in the Si1-y2Cy2 epilayers sample after annealing 900℃, possibility due to the formation of carbon-containing interstitial complexes.

並列關鍵字

Platinum Silicide Epi-SiC Thermal Stability

參考文獻


1.1 G. E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics 38, (1965).
1.3 M. Berti, D. D. Salvador, A. V. Drigo, F. Romanato, J. Stangl, S. Zerlauth, F. Schäffler, and G. Bauer, “Lattice Parameter in Si1-yCy Epilayers: Deviation from Vegard’s Rule,” Appl. Phys. Lett. 72, 1602-1604 (1998).
1.4 S. M. Koh, X. Wang, K. Sekar, W. Krull, G. S. Samudra, and Y. C. Yeo, “Silicon-Carbon Formed Using Cluster-Carbon Implant and Laser-Induced Epitaxy for Application as Source/Drain Stressors in Strained n-Channel MOSFETs,” J. Electrochem. Soc. 156, H361-H366 (2009).
1.5 P. C. Kelires, “Short-Range Order, Bulk Moduli, and Physical Trends in c-Si1-xCx Alloys,” Phys. Rev. B, 55, 8784 (1997).
1.6 F. Andrieu, O. Weber, T. Ernst, O. Faynot, and S. Deleonibus, “Strain and Channel Engineering for Fully Depleted SOI MOSFETs towards the 32 nm Technology Node,” Microelectron. Eng. 84, 2047-2053 (2007).

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