基於FPGA上針對多協定系統之高應用適應性可重組式快速傅立葉轉換處理器

FPGA-based High Applicability Reconfigurable FFT Processor for Multi-standard Systems

吳政謙(Cheng-Chien Wu)

指導教授 ： 熊博安

國立中正大學/工學院/資訊工程學系/碩士(2013年)

摘要

近五年來，因為科技的進步，使用者對於手持裝置的使用習慣有大幅度的改變。尤其是在無線通訊領域上的需求也變得不再單純，像是將手機當作無線基地台分享器就必須同時使用3G協定以及WIFI協定。抑或是使用手機觀看數位電視的同時仍使用WIFI瀏覽網路上的資訊，都必須同時支援多個協定(通訊與影像)。傳統上，同時支援多個協定必須使用多個快速傅立葉轉換(Fast Fourier Transform, FFT)運算元件，這樣並未有效率的使用FFT元件，造成硬體資源和電能的浪費。針對有效同時支援多個協定的議題，這篇論文提出一個新的可重組式FFT架構，稱作「高應用適應性可重組式快速傅立葉轉換 (High Applicability Reconfigurable FFT，簡稱HAR-FFT)」。HAR-FFT包含配置資源的軟體驅動和提供FFT計算的硬體。它主要是在不違反應用程式或協定的時間限制下，利用時間分割切換讓基本的FFT運算單元能夠在不同協定的應用程式間作切換。HAR-FFT也利用動態部分可重組支援不同點數的FFT。我們所提出的架構結合了管線式架構以及記憶體式架構兩種傳統架構的優點，並且能夠讓多個應用去共享硬體資源。我們在Xilinx Virtex 6 的FPGA上實作一個HAR-FFT的雛形架構。實驗和評估顯示，我們提出的架構比起管線化架構能夠平均減少超過50%以上的硬體資源，且效能仍高於記憶體式的架構，特定情況下的效能甚至可以逼近於管線式的硬體架構。

關鍵字

快速傅立葉轉換

並列摘要

In the last five years, due to the technology progress, mobile device usage has
undergone a radical change. Especially, the requirements for wireless communications
are no longer simple. For example, most smart mobile phones can be used as a WIFI
hotspot, thus there is a simultaneous need for both 3G and WIFI protocols. Another
example is when a user watches DTV on a mobile phone, while browsing on the internet
at the same time, which also demands the simultaneous execution of multiple
protocols (communication and video). Conventionally, multiple protocols need multiple
FFT components, which are not fully utilized and result in a waste of computing
resources and energy. To address this issue of efficient simultaneous support for multiple
protocols, this Thesis proposes a novel reconfigurable FFT architecture called High
Applicability Reconfigurable FFT (HAR-FFT). The HAR-FFT architecture includes
the software driver for resource allocation and the hardware device for computing
FFT. It is mainly based on time-division multiplexing for the basic radix blocks such
that they can multiplexed among several applications, without violating the time
constraints of the applications or standards. HAR-FFT also leverages dynamic partial
reconfiguration for supporting multiple sizes of FFT. HAR-FFT combines the
advantages of the conventional pipeline-based and the memory-based architectures
by sharing hardware resources among multiple applications. A working prototype of
HAR-FFT was implemented on Xilinx Virtex 6 FPGA device. Experiments and evaluations
show that compared with pipeline-based architecture HAR-FFT saves more
than 50% of hardware resources in average, and the performance is still higher than
the memory-based architecture. Even in specific conditions, the performance is very
close to the pipeline-based architecture.

並列關鍵字

Fast Fourier Transform ； FPGA ； Partial Reconfigurable Systems ； OFDM ； FFT

參考文獻

FPGA Devices. National Taipei University of Technology, Graduate

[11] C. H. Chang, C. L. Wang, and Y.-T. Chang. A Novel Memory-based FFT

[6] G. R. Hiertz, Y. Zang, S. Max, T. Junge, E. Weiss, and B. Wolz. Ieee 802.11 s:

Symposium on Communications and Information Technologies, pages 1507–1510,

October 2007.