自適性電壓調控指令快取記憶體設計研究

Study on Instruction Cache Design with Adaptive Voltage Scaling

周宏霖(Hong-Lin Chou)

指導教授 ： 林泰吉

國立中正大學/工學院/資訊工程學系/碩士(2013年)

摘要

自適性電壓調控已成功應用在處理器設計中，但仍未廣泛應用在靜態記憶體設計。本論文嘗試應用自適性電壓調控，尤其是超標降壓(voltage overscaling)技術於內嵌式記憶體之中。由於指令快取記憶體並非指令單一存放位置，過度降壓造成資料損毀仍可由次一層級之記憶體恢復，我們將此種情況歸類為”可靠度miss”進行探討，考量過度降壓造成資料損毀之額外記憶體存取能量，我們延伸標準之trace-based模擬方法，利用CACTI記憶體模型及65nm實作之SRAM模組實際測量錯誤率進行分析，分析可達到最佳能耗的標準電壓，針對實際應用之分析，我們更建構一FPGA功能模擬環境可大幅增加評估之速度。

關鍵字

低電壓的錯誤容忍cache ； AVS

並列摘要

Adaptive voltage scaling (AVS) has been successfully applied in energy-efficient microprocessor designs. However, the technique has not been widely used in memory (SRAM) designs. This thesis tries to adopt the AVS technique (especially with voltage overscaling ) in embedded memory systems. While encountering data losses due to overscaling the supply voltage of instruction caches, the cache line can be discarded & the instruction can be fetched from the next-level memory. The situation in regarded as “reliability miss” is our analysis. The optimal supply voltage is studied, considering the extra memory accessed due to reliability misses. We have extended traditional trace-based simulations for our evaluations. The CACTI model & a 65nm testchip are used for energy estimation. Beyond the trace-based simulations, FPGA environment has also been constructed for evaluating real workload.

並列關鍵字

Fault-tolerant cache in low voltage ； AVS

參考文獻

[1]: ITRS, “International Technology Roadmap for Semiconductors 2012.” http://www.itrs.net/Links/2012ITRS/Home2012.htm

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[4]: M. Shareef, P. Nair, and B. Amrutur, "Energy reduction in SRAM using dynamic voltage and frequency management," in Proc. VLSI, 2008, pp.503-508.

[5]: M. Farahani and A. Baniasadi, “Performance and power solutions for caches using 8T SRAM cells,” in Proc. ACM, 2012, pp. 74-80.