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  • 學位論文

可操作於 1GHz至3GHz之全數位、抗變異、低功耗、高解析度時脈抖動量測電路

On-Chip All-Digital Low-Power High Resolution Jitter Measurement Circuit with High Variation-Tolerant Working on 1GHz to 3GHz

指導教授 : 王進賢
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摘要


系統單晶片(System-on-chip)已然是現今以及未來積體電路發展的主要趨勢,而當不同電路整合在同一塊晶片上時,電路間在時序上的控制必須十分精準,大多數的系統單晶片採用鎖相迴路(Phase-Locked Loop, PLL)作為參考訊號產生來源,若鎖相迴路輸出訊號帶有過大抖動量,也會造成整體系統數值存取錯誤,但隨著現今電路操作頻率不斷提升,時脈抖動量數值變的十分細微,若想利用外部儀器量測時脈抖動量,不僅要耗費高成本,量測過程中也可能遇到雜訊干擾,使得量測失真,為了準確量測時脈抖動,進而發展了內建式時脈抖動量測電路。 本論文提出「可操作於1GHz至3GHz之全數位、抗變異、低功耗、高解析度時脈抖動量測電路」,本論文電路以高應用面、高解析度、可抵抗製程變異、不須輸入額外參考時脈以及低功耗為設計重點。本碩士論文利用自我取樣技巧消除需要額外輸入參考時脈這項條件,搭配可調整式延遲線將輸入頻率拓寬,並搭配校正電路提高製程抵抗力,除此之外為了提高量測精準度,使用數位放大技巧提高解析度。 可操作於1GHz至3GHz之全數位、抗變異、低功耗、高解析度時脈抖動量測電路使用UMC 28nm以及TSMC 28nm製程實現,輸入頻率可量測1GHz至3GHz,整體電路解析度0.59ps,消耗功率約0.62mW,晶片面積約為0.0032mm2。

並列摘要


System on chip has been a major development of the VLSI circuit. When many different circuits into a chip, the timing between circuits and circuits must be controlled accurately. PLL circuit is used to generate the source clock in the SoC system. If the clock jitter of the PLL circuit become too much, the mistakes of system operation will be generated. But it is difficult to measure the output clock jitter of the PLL circuit accurately by using external measuring equipments. It not only need to take the high cost of equipment but also the noise may cause that the measured result is not true to the original. For all these reasons, the built-in jitter measurement is be produced. The features of the On-Chip All-Digital High Resolution Jitter Measurement Circuit with High Variation-Tolerant working on 1GHz to 3GHz are high application, high-resolution, process variation, low power and without reference clock. This proposed circuit use self-sampling technique to eliminate the requirement of the reference clock and Calibration circuit to promote the process variation tolerance. in addition, this proposed circuit uses the time amplifier circuit to increase the high accuracy. The On-Chip All-Digital Low-Power High Resolution Jitter Measurement Circuit with High Variation-Tolerant working on 1GHz to 3GHz is designed in UMC 28nm process and TSMC 28nm process. The operating frequency range of this proposed circuit is from 1GHz to 3GHz. The total resolution of this proposed circuit is 0.59ps, power consumption is 0.62mW and the area of the chip is 0.0032mm2.

參考文獻


[1] 龔彥中 撰, 題目:數位電路傳輸品質之統計評量, 國立中央大學, 中華民國九十六年 七月.
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[8] J. Yu and F.F. Dai, “On-chip Jitter Measurement Using Vernier Ring Time-to-Digital Converter,” Asian Test Symposium(ATS), pp. 167-170, Dec. 2010.

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