自時系統的超大型標準元件庫設計與實作

Design and Implementation of VLSI Cell Library for Self-timed Systems

楊智文(Chih-Wen Yang)

指導教授 ： 鄭福炯

大同大學/電機資訊學院/資訊工程學系所/碩士(2005年)

摘要

非同步電路能夠降低耗能，提高系統效能。省電、高效能的非同步電路已經逐漸受到重視，然而目前無自動化的設計流程可合成非同步電路。如果要實作出非同步超大型積體電路的晶片，有必要具備自時電路的超大型標準元件。這篇論文提出以自時電路的超大型標準元件庫設計與實作，來實作非同步超大型積體電路的晶片。 由實驗證明，當完全使用台積電的標準元件庫來合成非同步電路，在做pre-layout的電路模擬驗證正確，但做post-layout電路的模擬驗證時會產生錯誤的輸出。當完全使用我們自行設計的標準元件庫來合成非同步電路，在做電路的模擬驗證時可以得到正確的結果。但跟完全使用台積電的標準元件庫來合成非同步電路做pre-layout的比較，面積會增加3%左右，速度會慢10%左右。也由於台積電提供的基本元件，如AND、OR、NOT、XOR等等、其速度和面積都比我們自行設計的標準元件還理想，所以我們把自行設計的自時元件，如C-element、Toggle等等，搭配台積電的標準元件庫來合成非同步電路，跟完全使用台積電的標準元件庫來合成非同步電路做pre-layout的比較，在面積方面可以減少14%左右；在速度方面平均可以提升20%左右。

關鍵字

自時系統 標準元件庫

並列摘要

Asynchronous circuits have potentially the advantage of low-power consumption, modularity and high-performance. It is necessary to have self-timed cell library to implement asynchronous VLSI chips in current asynchronous design flows. This thesis presents the design and implementation of a self-timed VLSI cell library to facilitate automatic system-level synthesis.
From the results of our experiment, it is correct that we simulate and verify the circuits when synthesizing asynchronous circuits with TSMC standard cell library during pre-layout simulation. But we get incorrect output values when we simulate and verify the circuits in post-layout simulation. When we use our self-timed cell library to synthesize asynchronous circuits, we get correct results. But in pre-layout simulation the area will increase 3% and the speed will increase 10% in comparison with TSMC standard cell library. On the other hand, TSMC provides standard cells such as AND, OR, NOT and XOR, which area and speed are better than our designing standard cells. Therefore, we synthesize asynchronous circuits with our self-timed cells, such as C-element, Toggle, and TSMC standard cells. In pre-layout simulation the area reduces 14% and the speed improves 20% in comparison with TSMC standard cell library.

並列關鍵字

self-timed VLSI standard cell library

參考文獻

[1] J. K. Kees van Berkel, Marly Roncken, Ronald Saeijs, Frits Schalij, "The VLSI programming language tangram and its translation into handshake circuits,1991.

[4] Shu-Ming Chang. “Compiling Activity Diagram into Self-Timed systems in VHDL”, 2003.

[7] Shams, M.; Ebergen, J.C.; Elmasry, M.I.; Modeling and comparing CMOS implementations of the C-element. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 6, Issue 4, Dec. 1998

[8] K. v. Berkei, “Beware the isochronic fork,” Integration, The VLSI J., vol. 13, pp. 103–128, June 1992.

[9] Synopsys manual : Library Compiler User Guide: Modeling Timing and Power Technology Libraries.