在本篇論文中,我們提出以前饋式架構為基礎的可調式共振器之雙取樣三位元四階帶通差和調變器,並以1.5伏電壓的放大器來實現電路中的共振器。在前饋式架構中的共振器僅需處理量化雜訊,避免原始訊號經由電路上共振器的非線性所造成失真的影響。使用可調式共振器,可以針對寬頻或窄頻運用規格所需要的超取樣比值 (OSR) 調整架構上的參數,以選取雜訊轉換函數之最佳陷波 (notch) 頻率。此外,利用雙取樣技術,不但提高取樣頻率且可舒緩放大器速度上的規格要求。 整體實現是用MATLAB和SIMULINK模擬理想和非理想的系統層級架構,藉此得到最佳的參數值。接著利用Hspice作電晶體層級的模擬,使用1.5伏電壓及TSMC 0.18um CMOS 1P6M製程參數。此調變器的時脈頻率為40MHz (相當於80MHz的取樣頻率),輸入中心頻率為20MHz。在頻寬為5MHz (OSR=8),其訊雜比在輸入為-6dBFS是50.26dB;在頻寬為0.625MHz (OSR=64),其訊雜比在輸入同樣為-6dBFS是66.97dB,整體功率消耗為37mW。
In this thesis, we propose a double-sampling three-bit fourth-order band-pass delta-sigma modulator based on switched-capacitor (SC) tunable resonators. With the feedforward topology, the resonators only need to process quantization noise, which can prevent linearity of the input signal affected by resonators. The tunable resonator can be adjusted to obtain the optimum notch frequencies of the noise transfer function according to the bandwidth. Additionally, double-sampled technique provides a good method of increasing the sampling frequency without many efforts and relaxes the performance requirement of the operational amplifier. The design is carried out as follows. First, MATLAB and SIMULINK are used to simulate the ideal and non-ideal system-level topology, and the design parameters can be optimized. Then, the transistor level simulation is done by Hspice with TSMC 0.18um CMOS 1P6M models. The clock frequency of the modulator is 40MHz (effective frequency would be 80MHz), and the input center frequency is 20MHz. For a 1.5V supply, the SNR is 50.26dB and 66.97dB with -6dBFS input for bandwidth 5MHz (OSR=8) and bandwidth 0.625MHz (OSR=64), respectively. The power consumption is 37mW.
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