可適應性頻寬且穩定控制的快速鎖相迴路

AN ADAPTIVE BANDWIDTH AND STABLE CONTROL FOR FAST LOCKED PLL

王健祐(Chien-Yu Wang)

指導教授 ： 蔡明傑

大同大學/電機資訊學院/電機工程學系所/碩士(2008年)

摘要

在設計鎖相迴路有幾個重要的問題要考慮的是：1.低抖動(Low-jitter) 2.低功率消耗(Low-power) 3.較寬的線性區範圍(Linearity region) 4.快速鎖定(Fast-locked)，本論文的設計則著重在快速鎖定上。
因此提出一個可適應性控制偵測電路之類比鎖相迴路架構，以一個新的適應性控制迴路的頻寬並且穩定的有效降低鎖定時間與低抖動特性，而且此可適性特色是藉由鎖定的狀況去做電流上的控制進而影響改變頻寬。
本篇論文所使用的製程為 TSMC 0.18 1P6M CMOS的技術，其鎖定時間約為800ns，鎖定時間比傳統鎖相迴路降低了50%以上，在功率消耗上約為23mW, 鎖相迴路的抖動大小約為24ps在2GHz的輸出頻率上.

關鍵詞：適應性, 快速鎖定, 低抖動, 鎖相迴路.

關鍵字

鎖相迴路 ； 低抖動 ； 快速鎖定 ； 適應性

並列摘要

To design a PLL must consider several conditions as the following：1. Low-jitter. 2. Low-power. 3. Wider linearity region. 4. Fast-locked. The thesis focuses on Fast-locked.
Therefore, this thesis presents the analog adaptive PLL architecture with a new adaptive controlled detector to reduce locking time and low jitter in PLL stably. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status.
The proposed architecture is realized in a standard TSMC 0.18 1P6M CMOS technology. The locking time is approximately 800ns and is reduced over 50% than the conventional PLL, power consumption is about 23mW and jitter magnitude is about 24ps on 2GHz.

Keywords：adaptive, fast-locked, low jitter, PLL.

並列關鍵字

low jitter ； fast-locked ； adaptive ； PLL

參考文獻

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