採用無負載及運算放大器共享技術之一伏特十位元10MSample/s低功率管線式類比數位轉換器

A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES

邱佩欣(Pei-Hsin Chiu)

指導教授 ： 黃淑絹

大同大學/電機資訊學院/電機工程學系所/碩士(2010年)

摘要

本篇論文提出一個使用每級1.5位元架構的低功率、十位元、工作頻率為10MHz的類比數位轉換器。為了可以在一伏特的低電壓下正常工作，此轉換器使用可切換式運算放大器，並且搭配運算放大器共享和無負載的技術，來達到低功率消耗和小佈局面積的效果。本轉換器採用0.18um 1P6M CMOS製程，透過Hspice模擬，在輸入頻率為0.55MHz的情況下，SNDR為52.92dB，其總功率消耗為17.4mW。

關鍵字

運算放大器共享 ； 切換式運算放大器 ； 管線式類比數位轉換器 ； 無負載技術

並列摘要

In this thesis, a 10-bit 10MHz pipelined analog-to-digital converter (ADC) consisting of 1.5-bit/stage has been designed using TSMC 0.18-μm 1P6M CMOS process models. For realizing the pipelined ADC with 1V, an innovative circuit for multiplying digital-to-analog converter (MDAC) is accomplished with the switched-opamp technique without any multiplied voltage circuit or low-threshold process. Furthermore, this thesis proposes a novel pipelined stage by combining the opamp-sharing and loading-free techniques to reduce the capacitive loading and to improve the speed in low-voltage switch circuit. As a result, the proposed pipelined ADC can operate under low power supply and reduce the total power consumption.
The ADC has been simulated by HSPICE. The resulting peak signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 52.92 dB with sampling frequency of 10MHz at input frequency of 0.55MHz. Power consumption of this ADC is 17.4mW with 1V power supply.

並列關鍵字

loading-free ； opamp-sharing ； switched-opamp ； pipelined ADC

參考文獻

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[1] R. J. Baker, CMOS Mixed-Signal Circuit Design, Wiley-Interscience, 2002.