本論文以台積電 0.18μm 1P6M CMOS 製程來研製應用於802.11a WLAN 之5GHz CMOS低雜訊放大器(LNA)。為因應WLAN系統高線性度、低相位雜訊、高工作頻率等特性,本論文探討四種不同LNA架構的適用性。第一種為電感式源極退化架構(Inductively Source Degeneration),模擬時增益為20.6dB,雜訊指數為3.12dB,IIP3為-2.1dBm, 為-8.0dBm,16.3mW消耗功率。第二種為使用Butterworth濾波器架構,其增益為13.9dB,雜訊指數為2.99dB,IIP3為-0.6dBm, 為-1.1dBm,7.6mW消耗功率。第三種為疊接式(Cascode)加上串級式(Cascade)的低雜訊放大器架構,利用RLC共振線路,來達到最佳效能,其模擬增益為16dB、雜訊指數為2.62dB、IIP3為11.8dBm、 為6.0dBm,39.1mW的功率消耗。最後討論電流再用(Current-Reuse)架構,其增益為19.4dB,雜訊指數為2.34dB,IIP3為4.2dBm, 為2.0dBm,12.7mW消耗功率。考慮效能、功率消耗及佈局面積,我們選擇第四種架構為最後實現電路,其佈局面積為0.567 mm2。
This thesis presents the implementation of a 5GHz CMOS LNA for 802.11a WLAN (Wireless Local Area Network) RFIC in TSMC standard 0.18μm CMOS technology. To achieve the WLAN Specification, including high linearity and low phase noise, we have investigated four LNA architectures. First, an inductively source degeneration architecture has been implemented; it has 20.5 dB gain, 3.12 dB NF, -2.1 dBm IIP3, -8.0 dBm , and 16.3mW power consumption in simulation status. Second, an LNA based on the Butterworth filter architecture has been designed; it has 13.9 dB gain, 2.99 dB NF, -0.6 dBm IIP3, -1.0 dBm , and 7.6mW power consumption. The third architecture is a cascode-cascade LNA, utilizing RLC resonance circuit to improve the performance. It has 16.0 dB gain, 2.62 dB NF, 11.8 dBm IIP3, 6.0 dBm and 39.1mW power consumption. The last is a current-reuse architecture; it has 19.4 dB gain, 2.34 dB NF, 4.2 dBm IIP3, 2.0 dBm , and 12.7mW power consumption in simulation status. Taken the performance, chip area and power dissipation into account, the current-reuse architecture is chosen for the chip implementation, and its die area is about 0.567mm2.
為了持續優化網站功能與使用者體驗,本網站將Cookies分析技術用於網站營運、分析和個人化服務之目的。
若您繼續瀏覽本網站,即表示您同意本網站使用Cookies。