高壓0.18微米, 60V (SOI LDMOS)功率元件之研究

Development of a 0.18μm , 60V ,Power Device based on SOI LDMOS Technology

許瑜珊(Yu Shan Hsu)

指導教授 ： 楊紹明 ； 許健

亞洲大學/資訊學院/資訊工程學系碩士班/碩士(2008年)

摘要

利用絕緣層上覆矽的技術，可以解決改善發生在接面隔離技術的接面高漏電， 電路閂鎖問題，和高寄生電容，將一個CMOS 相容薄膜SOI 技術使其得到最好整合性能與成本，應用在未來的技術藍圖中LDMOS 元件的一項技術。本文主要模擬一個CMOS相容的薄膜的SOI LDMOS(橫向雙倍擴散的MOSFET)元件，通道長度0.18µm，0.02µm閘極氧化層和3µm N-Drift，模擬出最佳化的關閉狀態崩潰電壓(BVoff) 和啟使電阻 (Ron)。
利用二維的TCAD模擬出LDMOS製程(TSuprem-IV) 和元件的特性(Medici)， 這樣的模擬出一個優化的元件，崩潰電壓操作在80V，啟使電阻大約在227 Ω-mm2。 在開啟狀態下量測的崩潰電壓由源極到汲極的電流的崩潰電壓在60~90V並且操作在一個好的安全操作區間，得到一個分析結果被用來驗證電場和電位分佈得到的數值模擬。
關鍵字：

關鍵字

接面隔離(JI) ； 橫向擴散金氧半導體(LDMOS) ； 絕緣層上覆矽(SOI) ； 安全操作區間(SOA)

並列摘要

The high junction leakages, circuit latched issues, and high parasite capacitances happened in the device manufactured by junction isolation technology can be eliminated or improved if the device is manufactured by the thin SOI (Silicon-On-Insulator) technology. A CMOS compatible SOI technology with best tradeoff of performance and cost will be one of technologies used in the future roadmap of LDMOS devices. A CMOS compatible thin SOI LDMOS (Lateral Double-diffused MOSFET) device, with 0.18 micron gate length, 0.02 micron gate oxide and 5 micron N-drift region, is proposed to achieve the optimal (BVoff) off-state breakdown voltage and on-state resistance (Ron) values. The characteristics of the proposed LDMOS device are verified by the two-dimensional process simulator TSuprem-IV and the device simulator Medici. The simulated results have shown that a device performance at the range of BVoff, 80 v, and Ron, 100 mohm-mm2, is attended. The on-state breakdown voltage is measured at 70V with an excellent safe operating area (SOA) performance for the drain source current versus on-state breakdown voltage. An analytical solution is also used to verify the electrical field and potential distribution obtained by the numerical simulations.

並列關鍵字

Junction Isolation (JI) ； Lateral Diffused Metal–Oxide Semiconductor(LDMOS) ； Silicon-on-Insulator (SOI) ； Safe Operating Area (SOA)

參考文獻

【4】 王文翰，“熱載子效應在0.1μm短通道及2nm閘極薄氧化層SOI CMOSFET所造成特性退化之研究”，碩 士 論 文，June 2002。

【5】 Choul-Joo Ko, Sang-Yong Lee, Il-Yong Park, Cho-Eung Park, Bon-Keun Jun, Yong-Jun Lee,Chan-Hee Kang, Jae-O Lee, Nam-Joo Kim, and Kwang-Dong Yoo “Implementation of 85V High Side LDMOS with n-layer in a 0.35um BCD Process”，“IEEE Proceedings of the 20th International Symposium on Power Semiconductor Devices & IC's，No18-22,May 2008，pp103-104 .

Power LDMOS into a Low-Voltage 0.5 um BiCMOS Technology”，“IEEE IEDM NO Y2-27，1992，pp2.3.3”.

• 書籍

【1】原著/蕭宏、編譯/羅正中、張鼎張，2002，半導體製程技術導論，歐亞。