高電阻N-漂移區LDMOS元件的可靠性研究

Reliability Study of High Resistive N-drift Region LDMOS Device

蔡旻縉(Min-Chin Tsai)

指導教授 ： 許健

亞洲大學/資訊學院/資訊工程學系碩士班/碩士(2011年)

摘要

這篇文章提供一個方法去顯著的改善高電阻N型漂移區LDMOS元件的崩潰電壓和導通電阻, 利用源極電極下的PBL濃度和延伸閘極場板的長度 .PBL的目的是在減少藉由衝擊游離產生的基極電流的大小, 延伸的閘極場板將會把衝擊游離區從接近閘極端的N型漂移區表面移動到 P-body和 N型漂移區之間的接面. 由於N型漂移區的最大空乏區增加,因此崩潰電壓也跟著增加.

關鍵字

衝擊游離 ； 崩潰電壓 ； 導通電阻 ； 橫向擴散金屬氧化電晶體 ； 場板 ； 電腦輔助設計模擬

並列摘要

This article provides a method to significantly improve breakdown voltage and specific on-resistance in high resistivity drift region LDMOS by using PBL doping under the source terminal and the gate extended field plate technologies. The insertion of PBL aims at the reduction of bulk current caused by the impact-ionization-generated holes while the gate extended field plate will shift the impact ionization region from N-drift region surface near the gate side down towards the junction between the P-body and N-drift region and thereby increase the breakdown voltage due to the increase of maximum depletion in the N-drift region.

並列關鍵字

impact ionization ； breakdown voltage ； on-resistance ； LDMOS ； field plate ； TCAD simulation

參考文獻

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