Anello：適用於64核心之多核心互聯網路之可合成Verilog設計

Anello: a New Multicore Interconnection Network for 64-cores Architecture by Using Synthesizable Verilog HDL

朱守禮(Slo-Li Chu) ； 李耕學(Geng-Siao Li) ； 吳庭萱(Ting-Xuan Wu)

《先進工程學刊》 7卷4期 (2012/10) Pp. 193-202

https://doi.org/10.29948/JAE.201210.0008

摘要

近年來，由於電腦系統吞吐量的需求快速增加，使得多核心系統所包含的核心數量也隨之快速增長，致使核心間互聯網路複雜度增加，進而拉長了核心間的傳輸延遲。因此，多核心架構之互連網路設計即成為影響效能的主要因素。有鑑於此，本論文提出一個適用於64核心多核心架構的新式互聯網路，稱為Anello。Anello以環狀互聯網路為設計基礎，加上Cluster概念，將存取分為內部與外部兩種。系統以環狀互聯網路連接16個Clusters，每個Cluster連接一個Forwarder、一個AGENT、四個處理器及一個記憶體，因此當核心數量擴充時，將可以四倍數成長。本研究使用RTL Verilog實現16 Cores的Anello互連網路，並以Mentor Graphics ModelSim Verilog模擬器模擬設計之功能性、並以Novas nLint進行可合成設計之語法校正。在使用Synopsys Design Compiler，並以TSMC 0.13μm製程技術合成後，Anello 之工作頻率可達到400MHz。

關鍵字

多核心處理器 ； 晶片網路 ； 環狀拓樸 ； 互連網路

並列摘要

The continuous growing in the throughput requirement from modern computer makes more cores integrated into multicore chips. The latency to transfer delay from inter-core communication in these systems is dramatically increased due to the complexity of interconnection network. In this paper, a novel interconnection network, Anello, is proposed to solve the above problem. Anello adopts Ring structure and Cluster structure as the local networks and global networks respectively. The Ring structure, which connects 16 Clusters, provides the infrastructure of inter-Cluster communication and every Cluster is composed by a Forwarder, an AGENT, four processors, and a memory module. Therefore, the scalability of Anello can be fourtimes grown up when the cores multiplied. By using synthesizable RTL Verilog HDL, the implementation of Anello with the configuration of 16 cores is functionally verified by Mentor Graphics Modelsim simulator, and the coding for synthesizing is also checked by Novas nLint. Furthermore, by using Synopsys Design Compiler, the result of Anello fabrication shows that it can achieve 400 MHz under TSMC 0.13 μm process technology library.

並列關鍵字

multicore processor ； network-on-chip ； ring topology ； interconnection network