透過您的圖書館登入
IP:3.145.191.214
  • 期刊
  • OpenAccess

RNS數位濾波器容錯技術之研究

A Study on Fault-Tolerant Techniques for RNS Digital Filters

摘要


餘數系統(Residue Number System: RNS)的特殊代數結構,使RNS-based arithmetic Processor在硬體寶現無易具有模組性與平行性,而此二特性在應用超大型積體電路(VLSI)技術是非常重要的,本研究將在餘數系統上發展-糾單錯之超高速演算法,根據此演算法設計適合RNS-based FIR及RNS-based DCT濾波器之容錯硬體架構,預期在容錯硬體的複雜性(Hardware Complexity)約是O(k),而目前所知之其他硬體複雜性約在O(k^2),複雜性是就運算速度與所需加乘運算量而言。

並列摘要


The modular algebraic structure of the residue number systems (RNS) leads to modularity and parallelism in the hardware implementation for the RNS-based arithmetic processor. Both modularity and parallelism are essential to fully utilize the very-large-scale integrated (VLSI) technology. In this study, a superfast algorithm for correcting single residue errors in the RNS is developed with a slight increase in redundancy. Based on this algorithm, architectures for implementation of RNS-based FIR and RNS-based DCT filters are proposed. The hardware complexity for this superfast algorithm is O(k) while the hardware complexity for previous known algorithms is O(k^2).

並列關鍵字

RRNS-PC algorithm fault tolerance FIR DCT

延伸閱讀