矽深蝕刻中RIE LAG效應之消除

Eliminating of RIE LAG Effect in deep Silicon Etching

陳秀香(Hsiu-Hsiang Chen)

《光學工程》 87期 (2004/09) Pp. 55-60

https://doi.org/10.30011/OE.200409.0007

摘要

本論文使用SF6-O2-CHF3電漿氣體研究深矽溝槽的活性離子蝕刻延遲效應。調整O2和CHF3在SF6-O2-CHF3氣體中的濃度，可得到垂直的蝕刻圖形而且沒有活性離子蝕刻延遲效應（蝕刻深度與線寬大小無關）。實驗結果得到在5μm到40μm線寬的溝槽可得到相同的蝕刻深度，最佳化條件如下：ICP功率150watt、氣體壓力100mtorr、27%O2 in SF6-O2混合、33%CHF3 in SF6-O2-CHF3混合。目前實驗的結果已可得到20μm的垂直矽溝槽結構，而且與線寬大小無關（線寬由5μm到40μm）。

關鍵字

活性離子蝕刻延遲 ； 與深寬比有關的蝕刻率 ； 保護層

並列摘要

In this paper we study the RIE lag effect in deep silicon dry etching by employing a combination of fluorine-based RIE plasma (SF6/O2/CHF3). By adjusting the O2 and CHF concentration in SF6-O2-CHF3, we can obtain vertical and RIE lag free (the etching depth is independent of the line-width) structures. presented results show zero depth variation between 5μm and 40μm width with good uniformity. The optimum conditions are as follow: ICP power is 150watt gas pressure is 100mtorr 27%O2 in SF6-O2 mixtures 33%CHF3 in SF5-O2-CHF3 mixtures. We can obtain 20μm vertical silicon etching depth independent of the line-width (with the line-width from 5 μm to 40 μm).

並列關鍵字

RIE lag ； ARDE ； passivator