第四代行動通訊渦輪碼編解碼器之二次置換多項式交織器架構設計

Architecture Design of Quadratic Permutation Polynomial Interleaver for 3GPP LTE Turbo Encoding and Decoding

李順吉(Shuenn-Ji Lee)

《電腦與通訊》 130期 (2009/12) Pp. 73-78

https://doi.org/10.29917/CCLTJ.200912.0010

摘要

QPP(Quadratic Permutation Polynomail)交織器(Interleaver)由於具有記憶體平行存取非競爭(Contention-free)的特性，已被選定為第四代行動通訊規範(3GPP LTE)中渦輪碼的交織器。QPP交織器除了能避免渦輪解碼器內部記憶體平行存取時碰撞的問題之外，在硬體的複雜度及解碼速度上皆有不錯的表現。然而傳統上QPP交織器於渦輪碼編解碼器的硬體實現上仍存在兩類問題，即查表法(Memory based)交織器其面積過大與即時計算法(On-line calculation)之驅動時脈頻率過高等現象。據此，本文將提出以多個遞迴單位(Recursive Units)所組成的平行交織器硬體架構設計，同時解決傳統上交織器面積過大及交織器驅動時脈頻率過高的問題。本文中首先介紹渦輪碼編解碼器的架構，接著介紹QPP交織器的原理，於推演出低複雜度的硬體電路設計後，再將之置於LTE渦輪碼編解碼器架構中，同時再分析並提出該渦輪碼編解碼器硬體實現上可行的做法。

關鍵字

二次置換多項式 ； 渦輪碼 ； 長期演進

並列摘要

The QPP (Quadratic Permutation Polynomial) interleaver has the main advantage of contention-free for parallel memory access and has been adopted as the Turbo interleaver of 3GPP LTE. Besides the contention-free property, the QPP interleaver has low complexity and high decoding throughput for hardware realization. Meanwhile, conventional hardware designs of QPP interleaver have two major problems of large chip area and high clock rate. This article proposes a hardware architecture containing multiple recursive units which provide parallel interleaver outputs to solve the above problems of the conventional designs. In this article the architectures of turbo encoder and decoder will be introduced. The algebraic construction of QPP interleaver is also reviewed. The proposed parallel QPP interleaver design is then derived. The probable realization of the turbo encoder and decoder with proposed QPP interleaver architecture will be shown at the last section.

並列關鍵字

Quadratic Permutation Polynomial ； Turbo code ； Long Term Evolution