使用可變電容為基礎的殘餘值放大器的平行切換管線式循序漸進類比數位轉換器的分析與設計

Design and Analysis of a Parallel Conversion Pipelined-SAR ADC with Varactor Based Residue Amplifier

林東澄(Tung-Cheng Lin)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202100320

摘要

隨著5G世代的來臨，高速和高解析度的類比數位轉換器已經成為了不可或缺的部分。傳統的逐次逼近類比數位轉換器架構雖然可以達到中等解析度和和很高的電源節省效率，但整體的轉換速度會受到其漸進式的過程所限制；時間交錯系統類比數位轉換器能夠有效的提升逐次逼近類比數位轉換器的速度，但會有諸多的問題導致整體效能的下降，例如:取樣的相位誤差、通道的元件誤差、增益誤差......等。因此，電路中往往需要複雜的校正系統，言而總之，管線式逐次逼近類比數位轉換器成為了一個比較好的選擇。然而，傳統上的管線式逐次逼近類比數位轉換器在轉換過程中，需要留一段時間供給放大器所使用，使轉換速率下降。本篇即使用了能夠讓轉換過程與放大過程同時進行的技巧，解放了管線式逐次逼近類比數位轉換器的速度限制，此外，本篇還開發了一個壓變電容為基底的開迴路動態式放大器來改善線性度，使放大器能夠應付高達10位元的逐次逼近類比數位轉換器。本篇最後達到一個通道十位元、一億赫茲取樣頻率，在Nyquist輸入頻率下信噪失真比(SNDR)達41.34分貝、電源功耗為9.4毫瓦。

關鍵字

管線式逐次逼近類比數位轉換器 ； 開迴路動態式放大器 ； 高速

並列摘要

Along with 5G generations coming, high-speed and high-resolution analog - to - digital converters (ADCs) are the essential building blocks. Classical successive - approximation - register (SAR) ADC architectures can reach moderate resolution and high power efficiency, but the speed is limited by their serial decision-making process. Although the time-interleaved ADCs can really speed up the SAR ADC architectures, multiphase error, channel mismatch and gain error degrade the performance. Therefore, intensive calibration circuits are required. Alternatively, pipelined SAR architectures are the applicable choices. The conventional pipelined SAR ADCs need to reserve sufficient time for the residue amplifier. In this work, a technique that allows residue conversion and partial bit conversion in parallel is proposed in the pipelined SAR ADC to lessen timing constraint. Furthermore, a varactor-based dynamic amplifier is adopted to improve linearity for 10-b accuracy. The single channel prototype reaches 10-bit 1GS/s with SNDR 41.34dB at a Nyquist input consuming 9.4mW.

並列關鍵字

Pipelined-SAR ADC ； Dynamic amplifier ； High-speed

參考文獻

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