無需參考時脈之線性次包率時脈與資料回復電路

A Reference-Less Linear Sub-Baud-Rate Clock and Data Recovery Circuit

鄒墨(Mou Tzou)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202100321

摘要

本論文提出一個操作在6Gb/s到11Gb/s之無須參考時脈的線性次包率資料時脈回復電路，次包率之架構將可降低功率消耗，並因為利用混合訊號的操作方式，此電路將不需要依靠任何參考電壓來鎖定，另外此電路也包含頻率偵測之功能。此電路在資料速率為10Gb/s且通道耗損達到-8.6dB時功率消耗為8.66mW。

關鍵字

時脈與資料回復電路 ； CDR ； 次包率 ； RX ； 接收器

並列摘要

A 6Gb/s to 11Gb/s reference-less linear sub-baud-rate CDR is proposed to achieve low-power operation by employing a mixed-signal detection to obviate the need of the reference voltage. Furthermore, frequency acquisition can be merged into the same phase detector to aid the locking range. It can operate at the channel loss up to -8.6dB at Nyquist frequency with 8.66 mW power consumption, corresponding to the energy efficiency 0.86 pJ/bit at 10Gb/s.

並列關鍵字

Clock and data recovery ； CDR ； Sub-Baud-Rate ； RX ； Receiver

參考文獻

[1] B. Razavi, Design of CMOS PhaseLocked Loops. Cambridge University press, 2020.

[2] C.Hogge, “A Self-Correcting Clock Recovery Circuit,” IEEE J.Lightwave Technology., vol. LT3,no. 6, pp. 1312–1314, Dec. 1985.

[3] J. D. H. Alexander, “Clock Recovery From Random Binary Data,” Electronics Letters.,vol. 11, pp. 541–542, Oct. 1975.

[4] R.-J.Yang, S.-P.Chen, and S.-I.Liu, “A 3.125Gb/s Clock and Data Recovery Circuit for the 10-Gbase-LX4 Ethernet,” IEEE J. Solid-State Circuits, vol. 39, no. 8,pp. 1356–1360, Aug. 2004.

[5] W. Rahman, D. Yoo, J. Liang, A. Sheikholeslami, H. Tamura, T. Shibasaki, and H. Yamaguchi, “A 22.5-to-32Gb/s 3.2-pJ/b Reference-less Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS,” IEEE J. Solid-State Circuits, vol. 52, no. 12, pp. 3517–3531, Dec. 2017.