具備防禦能量旁通道攻擊之低成本數位線性穩壓器之設計與實作

Design and Implementation of a Low-Cost Digital Low-Dropout Regulator with Power Side-Channel Attack

程士豪(Shih-Hao Cheng)

指導教授 ： 劉宗德

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202100944

摘要

加密硬體會透過電源供應洩漏旁通道的物理資訊，而目前的防禦方法很多像是著重降低洩漏資訊的訊雜比或是能量等化和邏輯閘層次的遮蔽，很多現有設計都帶來了額外過多的面積或是能量耗損。本論文提出了一個防禦能量旁通道攻擊的低額外耗損數位線性穩壓器，此電路包含了進階加密標準電路(AES-128)以及負責穩壓AES且具有防禦旁通道攻擊的數位線性穩壓器。在本設計中，藉由搭配切換電容的電流幫補以低功耗低面積來防禦旁通道攻擊以及降低穩壓漣波，讓整體設計符合物聯網終端加密裝置的需求。
此電路使用0.18um CMOS製程製作，其所占的面積為4 mm2。整體面積相對於AES-128的面積額外佔18%，能量的額外消耗是8.2%，整體系統包含AES-128操作在50MHz，且在相關功率攻擊(CPA)下經過126K次加密的仍然安全未被破密成功。

關鍵字

進階加密標準 ； 相關性能量分析 ； 集成的電壓穩壓器 ； 能量旁通道攻擊

並列摘要

Cryptographic hardware leaks significant “side-channel” information through their power supplies. The existing power side-channel attack (PSCA) countermeasures are mainly based on reducing the signal-to-noise ratio (SNR) of the leaked information, power balancing, or gate-level masking, each of which introduces significant power or area overheads. This thesis presents a low-overhead circuit, which includes an Advanced Encryption Standard (AES-128) engines as well as a digital low drop-out regulator (LDO) that achieves PSCA immunity.
The proposed circuit is implemented in 0.18um CMOS process and occupies 4 mm2.
The total area and power overhead is 18%, 8.19%, respectively. The system implementation operates at 50MHz, and remains secure even after 126K encryptions.

並列關鍵字

Advanced Encryption Standard(AES) ； Correlation power analysis(CPA) ； integrated voltage regulator(IVR) ； power side-channel attack(PSCA)

參考文獻

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